参数资料
型号: NCP1650EVB
厂商: ON Semiconductor
文件页数: 2/31页
文件大小: 0K
描述: BOARD EVAL NCP1650 PFC CTLR
设计资源: NCP1650EVB Schematic
NCP1650EVB Bill of Materials
NCP1650EVB Test Procedure
NCP1650EVB Gerber Zip
标准包装: 1
主要目的: 电源管理,功率因数校正
嵌入式:
已用 IC / 零件: NCP1650
已供物品:
其它名称: NCP1650EVB-ND
NCP1650EVBOS
NCP1650
PIN FUNCTION DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
V CC
V ref
AC
Compensation
AC REF
AC Input
Feedback/
Shutdown
Loop
Compensation
P COMP
P MAX
I avg
I avgfltr
I S--
Ramp
Compensation
C T
Ground
Output
Description
Provides power to the device. This pin is monitored for undervoltage and the unit will not operate if the
V CC voltage is not within the UVLO range.
6.5 V regulated reference output. This reference voltage is disabled when the chip is in the shutdown
mode.
Provides pole for the AC Reference Amplifier. This amplifier compares the sum of the AC input voltage
and the low frequency component of the input current to the reference signal. The response must be slow
enough to filter out most of the high frequency content of the current signal that is injected from the
current sense amplifier, but fast enough to cause minimal distortion to the line frequency information.
This pin accommodates a capacitor to ground for filtering and stability of the AC error amplifier. The AC
error amplifier is a transconductance amplifier and is terminated with an internal high impedance load.
The rectified input AC rectified sinewave is connected to this pin. This information is used for the
reference comparator, maximum power circuit, and the average current compensation circuit.
The DC output of the converter is reduced through a resistive voltage divider, to a level of 4.0 V, and
connected to this pin to provide feedback for the voltage regulation loop. This pin also provides an input
undervoltage lockout feature by disabling the chip until the divided output voltage exceeds 0.75 V. It can
also be used as a shutdown pin by shorting it to ground with an open collector comparator, or a small
signal transistor.
A compensation network for the voltage regulation loop, is connected to the output of the voltage error
amplifier at this pin.
A compensation network for the maximum power loop, is connected to the output of the power error
amplifier at this pin.
This pin allows the output of the power multiplier to be scaled for the desired maximum power limit level.
This multiplier is a proprietary switching design and requires both a resistor and capacitor to ground. The
value of this resistor is determined in conjunction with R10.
An external resistor with a low temperature coefficient is connected from this terminal to ground, to set
and stabilize the gain of the Current Sense Amplifier output that drives the Power Multiplier and the AC
error amplifier. This resistor should be of the same type as that used on pin 9. The value of this resistor
will determine the maximum average current that the unit will allow before limiting will occur.
A capacitor connected to this pin filters the high frequency component from the instantaneous current
waveform, to create a waveform that resembles the average line current.
Negative current sense input. Designed to connect to the negative side of the current shunt.
This pin biases the ramp compensation circuit, to adjust the amount of compensation that is added to the
instantaneous current and AC error amp outputs.
Timing capacitor for the internal oscillator. This capacitor adjusts the oscillator frequency.
Ground reference for the circuit.
Drive output for power FET or IGBT. Capable of driving small devices, or can be connected to an external
driver for larger transistors.
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