参数资料
型号: NCP3121QPBCKGEVB
厂商: ON Semiconductor
文件页数: 19/41页
文件大小: 0K
描述: EVAL BOARD FOR NCP3121QPBCKG
设计资源: NCP3121 EVB BOM
NCP3121QPBCKGEVB Gerber Files
NCP3121QPBCKGEVB Schematic
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 2,非隔离
输出电压: 3.3V,5V
电流 - 输出: 3A,3A
输入电压: 12V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP3121
其它名称: NCP3121QPBCKGEVBOS
NCP3121
PLD devices) is drastically reduced. The failure is often a
result of high currents flowing to the pins or the high voltage
difference between pins.
In that case, the signal processors require multiple power
supplies generating different voltage levels for core and I/O
peripherals over time. NCP3121 offers ratiometric
sequencing, sequential sequencing and tracking sections to
manage the output voltages behavior during start ? up and
power ? down. Basically, the DSP, FPGA, and PLD
manufacturers do not specify the method of power
sequencing, but they do specify restrictions on the time or
voltage differences during power ? up and power ? down. The
power ? up sequence for microprocessors should be finished
approximately within a few seconds to prevent the risks
mentioned above. For more information, see the
microprocessor manufacturers’ datasheets.
Ratiometric Sequencing
In the ratiometric sequencing mode, multiple outputs start
ramping at the same time and also reach the regulation level
at the same time. When common EN is pulled down, the
output voltages are going down at the same time. See Figure
38. This functionality is created by using the same capacitor
values as the soft ? start capacitors for all outputs and by
connecting all EN + SEQ pins together. To ensure this
behavior, the soft start capacitors should have values greater
than the time constant of the output inductor and output
capacitor.
For proper operation in this mode, using a common
soft ? start capacitor for both channels is not recommended.
Note: If enable control is not required, float the EN/SEQ
connections rather than pulling them to VIN or a separate
supply voltage. The NCP3121 will enable itself once VIN
crosses the input UVLO threshold.
R_TRACK
AVIN
C3
C13
R13
C12
GND
VIN
OUT1
Disable
Enable
EN1
PG1
PG2
EN1
SEQ1
EN2
SEQ2
TRACK1
TRACK2
NCP3121
SW1
VIN
VIN
VIN
VIN
VIN
VIN
SW2
L11
D11
GND
C1
GND
L21
C2
GND
R11
R12
GND
C11
GND
OUT2
D21
GND
R21
C21
VOUT1
VOUT2
R_T
GND
C22
R23
C23
GND
GND
R22
GND
GND
Figure 38. Ratiometric Sequencing Configuration
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