参数资料
| 型号： | NCP5314MNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK CPU 2/3/4PH 32QFN |
| 产品变化通告： | Product Discontinuation 30/Jun/2004 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5314MNR2OSCT |
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NCP5314
loop system, the COMP pin would move higher to restore the
output voltage to the original level.
Inductive Current Sensing
For lossless sensing, current can be measured across the
inductor as shown in Figure 19. In the diagram, L is the
output inductance and R L is the inherent inductor resistance.
To compensate the current sense signal, the values of R CSx
and C CSx are chosen so that L/R L = R CSx ? C CSx . If this
criteria is met, the current sense signal should be the same
shape as the inductor current and the voltage signal at CSx
will represent the instantaneous value of inductor current.
Also, the circuit can be analyzed as if a sense resistor of value
R L was used.
SWNODE
R CSx
x = 1, 2, 3 or 4
Lx
C CSx
CSxP
+
CSA
COx
?
CSxN
RLx
V FFB
Internal Ramp
V OUT
(V CORE )
+
V FB
“Fast?Feedback”
Connection
?
Channel
Startup
Offset
+
?
PWM
To F/F
Reset
DAC
Out
E.A.
+
COMP
COMP
+
Figure 19. Enhanced V 2 Control Employing Lossless Inductive Current Sensing and Internal Ramp
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per ° C. The increase in
winding resistance at higher temperatures should be
considered when setting the OCSET threshold. If a more
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 17.
Current Sharing Accuracy
Printed Circuit Board (PCB) traces that carry inductor
current can be used as part of the current sense resistance
depending on where the current sense signal is picked off.
For accurate current sharing, the current sense inputs should
sense the current at relatively the same points for each phase.
In some cases, especially with inductive sensing, resistance
of the PCB can be useful for increasing the current sense
resistance. The total current sense resistance used for
calculations must include any PCB trace resistance that
carries inductor current between the CSxP input and the
CSxN input.
Current Sense Amplifier (CSA) input mismatch and the
value of the current sense component will determine the
accuracy of the current sharing between phases. The worst
case CSA input mismatch is ± 10 mV and will typically be
within 4.0 mV. The difference in peak currents between
phases will be the CSA input mismatch divided by the
current sense resistance. If all current sense components are
of equal resistance, a 3.0 mV mismatch with a 2.0 m Ω sense
resistance will produce a 1.5 A difference in current between
phases.
External Ramp Size and Current Sensing
The internal ramp allows flexibility in setting the current
sense time constant. Typically, the current sense R CSx ? C CSx
time constant should be equal to or slightly slower than the
inductor ’s time constant. If RC is chosen to be smaller
(faster) than L/R L , the AC or transient portion of the current
sensing signal will be scaled larger than the DC portion. This
will provide a larger steady?state ramp, but circuit
performance will be affected and must be evaluated
carefully. The current signal will overshoot during transients
and settle at the rate determined by R CSx ? C CSx . It will
eventually settle to the correct DC level, but the error will
decay with the time constant of R CSx ? C CSx . If this error is
excessive, it will affect transient response, adaptive
positioning and current limit. During a positive current
transient, the COMP pin will be required to undershoot in
response to the current signal in order to maintain the output
voltage. Similarly, the V DRP signal will overshoot which
will produce too much transient droop in the output voltage.
The single?phase pulse?by?pulse overcurrent protection
will trip earlier than it would if compensated correctly and
hiccup?mode current limit will have a lower threshold for
fast rising step loads than for slowly rising output currents.
http://onsemi.com
15
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