参数资料
| 型号： | NCP5314MNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 18/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK CPU 2/3/4PH 32QFN |
| 产品变化通告： | Product Discontinuation 30/Jun/2004 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5314MNR2OSCT |
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NCP5314
will be a 120 degree delay between pulses. The phase firing
order will become 1?2?3.
Two? and single?phase operation may be realized as well.
First, the designer must choose the proper phases. Two phase
operation must use phase 2 and 4 by tying CS1N, CS1P,
CS3N and CS3P to ground. This will then use phase 2 and
4 as the gate drivers. The other gate drives may switch, so
leave them unconnected.
Single phase is best accomplished by using only Phase 2
as the switch controller. Connect CS2P and CS2N pins to the
current sense capacitor and the gate drive to the driver IC.
Tie all other CSxx pins together and connect them to ground.
Table 1. Description of Fault Logic
Results
Stop
Driver
SS
Faults
Overvoltage Lockout
Enable Low
Module Overcurrent Limit
DAC Code = 11111x
V REF Undervoltage Lockout
PWRLS Out of Range
Switching
Yes
Yes
Yes
Yes
Yes
No
PWRGD Level
Low
Depends on output voltage level
Depends on output voltage level
Depends on output voltage level
Depends on output voltage level
Low
Enable
High
Low
Low
Low
Low
High
Characteristics
?0.3 mA
?0.3 mA
?0.3 mA
?0.3 mA
?0.3 mA
Not Affected
Reset Method
Power On
Not Affected
Power On
Valid VID
Power On
Not Affected
APPLICATIONS INFORMATION
1. Setting Converter Operating Frequency
The total resistance from R OSC to ground sets the
operating frequency for each phase of the converter. The
frequency can be set for either the three phase or four phase
Choose the number of bulk output capacitors to meet the
peak transient requirements. The formula below can be used
to provide a starting point for the minimum number of bulk
capacitors (N OUT,MIN ):
mode by using Figure 7, “Oscillator Frequency versus Total
R OSC Value.” After choosing the desired operating
frequency and the number of phases, use the figure to
NOUT,MIN + ESR per capacitor @
D IO,MAX
D VO,MAX
(1)
determine the necessary resistance. If two phase operation
is desired, use the value given for four phase operation.
The voltage from R OSC is closely regulated at 1 V. This
voltage can be used as the reference for the overcurrent limit
set point on the I LIM pin. Design a voltage divider with the
appropriate division ratio to give the desired I LIM voltage
and total resistance to set the operating frequency. Since
loading by the I LIM pin is very small, the frequency selection
will not be affected.
2. Output Capacitor Selection
The output capacitors filter the current from the output
inductor and provide a low impedance for transient load
current changes. Typically, microprocessor applications
require both bulk (electrolytic, tantalum) and low
impedance, high frequency (ceramic) types of capacitors.
The bulk capacitors provide “hold up” during transient
loading. The low impedance capacitors reduce steady?state
ripple and bypass the bulk capacitance when the output
current changes very quickly. The microprocessor
manufacturers usually specify a minimum number of
ceramic capacitors. The designer must determine the
number of bulk capacitors.
In reality, both the ESR and ESL of the bulk capacitors
determine the voltage change during a load transient
according to:
D VO,MAX + ( D IO,MAX D t) @ ESL ) D IO,MAX @ ESR (2)
Unfortunately, capacitor manufacturers do not specify the
ESL of their components and the inductance added by the
PCB traces is highly dependent on the layout and routing.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk capacitors and perform
transient testing or careful modeling/simulation to
determine the final number of bulk capacitors.
The latest Intel processor specifications discuss “dynamic
VID” (DVID), in which the VID codes are stepped up or
down to a new desired output voltage. Due to the timing
requirements at which the output must be in regulation, the
output capacitor selection becomes more complicated. The
ideal output capacitor selection has low ESR and low
capacitance. Too much output capacitance will make it
difficult to meet DVID timing specifications; too much ESR
will complicate the transient solution. The Sanyo 4SP560M
and Panasonic EEU?FL provide a good balance of
capacitance vs. ESR.
http://onsemi.com
18
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