参数资料
| 型号： | NCV3012DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 22/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 14TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 88kHz |
| 占空比： | 86% |
| 电源电压： | 4.7 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
NCP3012
Co RMS + I O @
I TRAN @ L OUT
D V OUT ? CHG +
V ESR_C + I O @ ra @ ESR Co )
ESL @ I PP @ F SW
V ESLON +
ESL @ I PP @ F SW
V ESLOFF +
Output Capacitor Selection
The important factors to consider when selecting an
output capacitor is dc voltage rating, ripple current rating,
output ripple voltage requirements, and transient response
requirements.
The output capacitor must be rated to handle the ripple
current at full load with proper derating. The RMS ratings
given in datasheets are generally for lower switching
frequency than used in switch mode power supplies but a
multiplier is usually given for higher frequency operation.
The RMS current for the output capacitor can be calculated
below:
ra
(eq. 20)
12
The maximum allowable output voltage ripple is a
combination of the ripple current selected, the output
capacitance selected, the equivalent series inductance (ESL)
and ESR.
The main component of the ripple voltage is usually due
to the ESR of the output capacitor and the capacitance
selected.
1
(eq. 21)
8 @ F SW @ Co
The ESL of capacitors depends on the technology chosen
but tends to range from 1 nH to 20 nH where ceramic
capacitors have the lowest inductance and electrolytic
capacitors then to have the highest. The calculated
contributing voltage ripple from ESL is shown for the switch
on and switch off below:
(eq. 22)
D
(eq. 23)
(1 * D )
The output capacitor is a basic component for the fast
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. It should be noted
that D VOUT ? DISCHARGE and D VOUT ? ESR are out of
phase with each other, and the larger of these two voltages
will determine the maximum deviation of the output voltage
(neglecting the effect of the ESL).
Conversely during a load release, the output voltage can
increase as the energy stored in the inductor dumps into the
output capacitor. The ESR contribution from Equation 21
still applies in addition to the output capacitor charge which
is approximated by the following equation:
2
(eq. 26)
C OUT @ V OUT
Power MOSFET Selection
Power dissipation, package size, and the thermal
environment drive MOSFET selection. To adequately select
the correct MOSFETs, the design must first predict its power
dissipation. Once the dissipation is known, the thermal
impedance can be calculated to prevent the specified
maximum junction temperatures from being exceeded at the
highest ambient temperature.
Power dissipation has two primary contributors:
conduction losses and switching losses. The control or
high ? side MOSFET will display both switching and
conduction losses. The synchronous or low ? side MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
non ? overlap time of the gate drivers.
Starting with the high ? side or control MOSFET, the
power dissipation can be approximated from:
P D_CONTROL + P COND ) P SW_TOT (eq. 27)
The first term is the conduction loss of the high ? side
MOSFET while it is on.
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
P COND + I RMS_CONTROL
2
@ R DS(on)_CONTROL (eq. 28)
I RMS_CONTROL + I OUT @
D @ 1 )
12
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initially
drops due to the current variation inside the capacitor and the
ESR (neglecting the effect of the effective series inductance
(ESL)).
D V OUT ? ESR + D I TRAN @ ESR Co (eq. 24)
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is
approximated by the following equation:
Using the ra term from Equation 9, I RMS becomes:
ra 2
(eq. 29)
The second term from Equation 27 is the total switching
loss and can be approximated from the following equations.
P SW_TOT + P SW ) P DS ) P RR (eq. 30)
The first term for total switching losses from Equation 30
includes the losses associated with turning the control
MOSFET on and off and the corresponding overlap in drain
voltage and current.
D V OUT ? DISCHG +
2
I TRAN @ L OUT
C OUT @ V IN * V OUT
(eq. 25)
P SW + P TON ) P TOFF
2
+ 1 @ I OUT @ V IN @ f SW @ t ON ) t OFF
(eq. 31)
http://onsemi.com
22
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