参数资料
| 型号： | NCV3012DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 14TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 88kHz |
| 占空比： | 86% |
| 电源电压： | 4.7 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
NCP3012
PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
VREF
EN
NC
SYNC
PG
COMP
FB
GND
LSDR
NC
VSW
HSDR
BST
V CC
Description
The VREF pin is the output for a 1.25 V reference (1 mA max). A 100 k W resistor in parallel with a 1 m F
ceramic capacitor must be connected from this pin to GND to ensure external reference stability.
The EN pin is the enable/disable input. A logic high on this pin enables the device. This pin has also an internal
current source pull up. A 10 k W resistor should be connected in series with this pin if V EN is externally biased
from a separate supply.
Not Connected
The dual function SYNC pin synchronizes the device to a higher frequency (Slave Mode). Alternately, it outputs
an 85 kHz clock signal with 180 ° of phase shift (Master Mode). Connect a 60 k W resistor from SYNC to GND
to enable Master Mode. No resistor is required for Slave Mode.
The Power Good pin is an open drain output that is low when the regulated output voltage is beyond the
“Power Good” upper and lower thresholds. Otherwise, it is a high impedance pin.
The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive
terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage
mode control feedback loop.
The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to
compensate the voltage mode control feedback loop.
Ground Pin
The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side
N ? FET. It is also used to set the threshold of the current limit circuit (I SET ) by connecting a resistor from LSDR
to GND.
Not Connected
The VSW pin is the return path for the high side driver. It is also used in conjunction with the V CC pin to sense
current in the high side MOSFET.
The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side
N ? FET.
The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the
VSW pin.
The V CC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current
in the high side MOSFET.
http://onsemi.com
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