参数资料
| 型号： | NCV3012DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 23/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 14TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 88kHz |
| 占空比： | 86% |
| 电源电压： | 4.7 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
NCP3012
I G1
I G2
where:
Q GD Q GD
t ON + + (eq. 32)
V BST * V TH R HSPU ) R G
and:
Q GD Q GD
t OFF + + (eq. 33)
V BST * V TH R HSPD ) R G
Next, the MOSFET output capacitance losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control MOSFET.
2
P DS + 1 @ Q OSS @ V IN @ f SW (eq. 34)
Finally the loss due to the reverse recovery time of the
body diode in the synchronous MOSFET is shown as
follows:
P RR + Q RR @ V IN @ f SW (eq. 35)
The low ? side or synchronous MOSFET turns on into zero
volts so switching losses are negligible. Its power
dissipation only consists of conduction loss due to R DS(on)
and body diode loss during the non ? overlap periods.
P D_SYNC + P COND ) P BODY (eq. 36)
Conduction loss in the low ? side or synchronous
MOSFET is described as follows:
2
P COND + I RMS_SYNC @ R DS(on)_SYNC (eq. 37)
I G1 : output current from the high ? side gate drive (HSDR)
I G2 : output current from the low ? side gate drive (LSDR)
? SW : switching frequency of the converter.
V BST : gate drive voltage for the high ? side drive, typically
7.5 V.
Q GD : gate charge plateau region, commonly specified in the
MOSFET datasheet
V TH : gate ? to ? source voltage at the gate charge plateau
region
Q OSS : MOSFET output gate charge specified in the data
sheet
Q RR : reverse recovery charge of the low ? side or
synchronous MOSFET, specified in the datasheet
R DS(on)_CONTROL : on resistance of the high ? side, or
control, MOSFET
R DS(on)_SYNC : on resistance of the low ? side, or
synchronous, MOSFET
NOL LH : dead time between the LSDR turning off and the
HSDR turning on, typically 85 ns
NOL HL : dead time between the HSDR turning off and the
LSDR turning on, typically 75 ns
Once the MOSFET power dissipations are determined,
the designer can calculate the required thermal impedance
for each device to maintain a specified junction temperature
at the worst case ambient temperature. The formula for
calculating the junction temperature with the package in free
air is:
( 1 * D) @ 1 )
I RMS_SYNC + I OUT @
where:
ra 2
12
The body diode losses can be approximated as:
P BODY + V FD @ I OUT @ f SW @ NOL LH ) NOL HL
Vth
(eq. 38)
(eq. 39)
T J + T A ) P D @ R q JA
T J : Junction Temperature
T A : Ambient Temperature
P D : Power Dissipation of the MOSFET under analysis
R q JA : Thermal Resistance Junction ? to ? Ambient of the
MOSFET’s package
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading, and component
variations (i.e. worst case MOSFET R DS(on) ).
Figure 34. MOSFET Switching Characteristics
http://onsemi.com
23
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