参数资料
| 型号： | NCV7240DPR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/26页 |
| 文件大小： | 0K |
| 描述： | IC DVR RELAY 8CH LOW SIDE 24SSOP |
| 标准包装： | 2,500 |
| 系列： | * |
NCV7240
TER Information Retrieval
TER information retrieval is as simple as bringing CSB high?to?low. No clock signals are required.
CSB
SI
MSB
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
B0
SCLK
SO
TER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 27. Serial Peripheral Interface
The timing diagram highlighted in Figure 27 shows the SPI interface communication.
Note:
1. The MSB (most significant bit) is the first transmitted bit.
2. Data is sampled from SI on the falling edge of SCLK
3. Data is shifted out from SO on the rising edge of SCLK
4. SCLK should be in a low state when CSB makes a transition.
Frame Detection
Input word integrity (SI) is evaluated by the use of a frame consistency check. The word frame length is compared to an
n * 8 bit (where n is an integer) acceptable word length (16?bit minimum) before the data is latched into the input register. This
guarantees the proper word length has been imported and allows for daisy chain operation applications with 8?bit SPI devices.
The frame length detector is enabled with the CSB falling edge and the SCLK rising edge.
Reference the valid SPI frame shown below. (Figure 27)
Frame detection mode ends with
CSB
SCLK
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
CSB rising edge.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SI
Internal Counter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Valid 16 bits shown
Figure 28. Frame Detection
DAISY CHAIN SETUP
http://onsemi.com
19
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