参数资料
型号: NCV7240DPR2G
厂商: ON Semiconductor
文件页数: 21/26页
文件大小: 0K
描述: IC DVR RELAY 8CH LOW SIDE 24SSOP
标准包装: 2,500
系列: *
NCV7240
8?bit Devices
The NCV7240 is also compatible with 8 bit devices due to the features of the frame detection circuitry. The internal bit
counter of the NCV7240 starts counting clock pulses when CSB goes low. The 1st valid word consists of 16 bits and each
subsequent word must be comprised of just 8?bits (reference the Frame Detection Section).
Compatibility
CSB SCLK
IC2
NCV7240
CSB SCLK
IC1
Any IC
using 8 Bit
SPI
protocol
The NCV7240
is also
compatible with
8?bit devices
Note the SCLK timing requirements of the NCV7240.
Data is sampled from SI on the falling edge of SCLK.
Data is shifted out of SO on the rising edge of SCLK.
Devices with similar characteristics are required for
operation in a daisy chain setup.
SI
SO
SI
SO
Figure 31. Serial Daisy Chain with 8?bit Devices
Parallel Connection
A more efficient way (time focused) to control multiple SPI compatible devices is to connect them in a parallel fashion and
allow each device to be controlled in a multiplex mode. Figure 32 shows a typical connection between the microprocessor or
microcontroller and multiple SPI compatible devices. In a serial daisy chain configuration, the programming information for
the last device in the serial string must first pass through all the previous devices. The parallel control setup eliminates that
requirement, but at the cost of additional control pins from the microprocessor for each individual CSB (chip select bar) pin
for each controllable device. Serial data is only recognized by the device that is activated through its’ respective CSB pin.
Figure 33 shows the waveforms for typical operation when addressing IC1.
NCV7240
SI
SCLK
SI
SCLK
IC1
CSB1
OUT2
SO
CSB OUT1
SO
CSB
OUT3
CSB2
chip1
NCV7240
CSB
chip2
SI
SCLK
IC2
OUT2
OUT2
CSB
chip3
CSB OUT1
SO
OUT3
NCV7240
IC3
SI
SCLK
CSB OUT1
SO
CSB3
SCLK
Figure 32. Parallel Connection
OUT3
SI
Figure 33. Parallel Connection Timing Diagram
http://onsemi.com
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