参数资料
型号: NCV7513BFTR2G
厂商: ON Semiconductor
文件页数: 7/23页
文件大小: 0K
描述: IC PREDRIVER HEX LOW SIDE 32LQFP
标准包装: 2,000
系列: *
NCV7513B
ELECTRICAL CHARACTERISTICS (continued) (4.75 V v V CCX v 5.25 V, V DD = V CCX , ? 40 ° C v T J v 125 ° C, unless otherwise
specified.) (Note 6)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Fault Detection – GAT X OFF
DRN X Diagnostic Current
DRN X Fault Threshold Voltage
DRN X Off State Bias Voltage
I SG
I OL
V SG
V OL
V CTR
Short to GND Detection,
V DRNX = 0.30 V CC1
Open Load Detection,
V DRNX = 0.75 V CC1
Short to GND Detection
Open Load Detection
?
? 27
30
27
72
? 20
60
30
75
50
? 10
80
33
78
m A
m A
%V CC1
%V CC1
%V CC1
Gate Driver Outputs
GAT X Output Resistance
GAT X High Output Current
GAT X Low Output Current
Output High or Low
V GATX = 0 V
V GATX = V CC2
1.0
? 5.25
1.9
1.80
2.5
? 1.9
5.25
k W
mA
mA
Turn ? On Propagation Delay
Turn ? Off Propagation Delay
Output Rise Time
t P(ON)
t P(OFF)
t R
IN X to GAT X (Figure 4)
CSB to GAT X (Figure 5)
IN X to GAT X (Figure 4)
CSB to GAT X (Figure 5)
20% to 80% of V CC2 ,
1.0
1.0
1.40
m s
m s
m s
C LOAD = 400 pF
(Figure 4, Note 5)
Output Fall Time
t F
80% to 20% of V CC2 ,
1.40
m s
C LOAD = 400 pF
(Figure 4, Note 5)
Fault Timers
Channel Fault Blanking Timer
Channel Fault Filter Timer
Global Fault Refresh Timer
(Auto ? retry Mode)
Timer Clock
t BL(ON)
t BL(OFF)
t FF
t FR
V DRNX = 5.0 V; IN X rising to
FLTB falling (Figure 6)
V DRNX = 0 V; IN X falling to
FLTB falling (Figure 6)
Figure 7
Register 2: Bit R 2 = 0 or R 5 = 0
Register 2: Bit R 2 = 1 or R 5 = 1
ENA1 = 1
30
90
7.0
7.5
30
45
120
12
10
40
500
60
150
17
12.5
50
m s
m s
m s
ms
ms
kHz
Serial Peripheral Interface (Figure 9) V ccx = 5. 0 V, V DD = 3.3 V, F SCLK = 4.0 MHz, C LOAD = 200 pF
SO Supply Voltage
SCLK Clock Period
Maximum Input Capacitance
SCLK High Time
SCLK Low Time
Sl Setup Time
V DD
3.3 V Interface
5.0 V Interface
?
Sl, SCLK (Note 7)
SCLK = 2.0 V to 2.0 V
SCLK = 0.8 V to 0.8 V
Sl = 0.8 V/2.0 V to
3.0
4.5
125
125
25
3.3
5.0
250
3.6
5.5
12
V
V
ns
pF
ns
ns
ns
SCLK = 2.0 V (Note 7)
Sl Hold Time
SCLK = 2.0 V to
25
ns
Sl = 0.8 V/2.0 V (Note 7)
6. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
7. Guaranteed by design.
http://onsemi.com
7
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