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参数资料
| 型号： | NHI-1598ET/883 |
| 厂商： | NATIONAL HYBRID INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封装： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件页数： | 16/89页 |
| 文件大小： | 569K |
| 代理商： | NHI-1598ET/883 |
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22
RES
Bits: 13, 9, 8
BC/ MT/ RT
This field defines the resolution of the RTC in microseconds as follows:
RESOLUTION(us)
13
9
8
1
0
2
0
1
4
0
1
0
8
0
1
16
1
0
32
1
0
1
64
1
0
OFF/EXT
1
Note: Some NHi- ET device types have an external TIME TAG CLOCK input.
M1760
Bits: 7
RT
1= Specifies that the RT shall comply with MIL- STD- 1760A. This mode of operation has two
consequences: first, the mode command "Synchronize With Data" updates the lower 16 bits
of the RTC only if the least significant data bit is "0" and second, the IPO_ DSC pin serves as
a store disconnect signal rather than an interrupt priority output.
0= Specifies that the RT shall comply with MIL-STD-1553B.
BUSY _OPT
Bits: 6
RT
0= MRST, Software Reset and MODE CODE_ 08 RESET will set the BUSY bit in the LAST
STATUS REGISTER and the BASIC STATUS REGISTER to a "1".
1= Only MRST will set the BUSY bit in the LAST STATUS REGISTER and the BASIC STATUS
REGISTER to a "1".
RESET BUSY
Bits: 5
RT
When a "1" is written to RESET BUSY, the BUSY bit in the LAST STATUS REGISTER is set to
a "0". The contents of the register are not affected by this operation and RESET BUSY is always
read by the host as "0".
PRESET
Bits: (4: 0)
RT
These bits provide a method to perform a double word( 32 bit) preset to the RTC. When this bit
field is set to any number from 1 to 30( bit 0 = LSB), the first two words of a receive message
whose subaddress is equal to this value will be used to preset the internal RTC. The most
significant word is received first. If this field is equal to a "0" or "31", the RTC will not be preset.
All bits in this register are cleared during initialization of the ET.
4.2.11
FIFO READ
Address: 8
R
BC/ MT/ RT
This address is used to read the contents of the interrupt FIFO. Reading this address pops the
FIFO, updates the IVR and the AVR; then outputs the AVR(upper byte) and IVR(lower byte).
4.2.12
FIFO RESET
Address: 8
W
BC/ MT/ RT
Writing any value to this address empties the FIFO.
4.2.13
LAST COMMAND REGISTER
Address: 11
R
RT
This register holds the last command word as defined by the MIL-BUS. The contents are not
defined after initialization of the RT.
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