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| 型号： | NHI-1598ET/883 |
| 厂商： | NATIONAL HYBRID INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封装： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件页数： | 5/89页 |
| 文件大小： | 569K |
| 代理商： | NHI-1598ET/883 |
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12
3.3.4
DUAL REDUNDANT FRONT END
The DRFE performs serial to parallel and parallel to serial conversion as well as basic format and
timing validation. The unit contains the following:
Manchester encoders/ decoders
Gap counter
No response counter
Minimum response time counter
Timeout counter
3.3.4.1
MANCHESTER DECODER
The decoder translates serial Manchester bi- phase signals to 16- bit words and outputs the
following signals:
Valid command word received
Valid data word received
Invalid word received (parity, incorrect bit count, invalid Manchester encoding, gap)
Broadcast command received
Begin new message (i. e., end of a valid legal command for this Remote Terminal)
3.3.4.2
MANCHESTER ENCODER
The encoder receives 16 bit words and transmits them with the appropriate sync and parity as a
serial Manchester bi- phase signal. The outputs of the encoder can be loop- backed into either
decoder for test purposes.
3.3.4.3
GAP COUNTER
The gap counter checks contiguity of successive words. If the time between "contiguous" words
(measured from zero- cross of parity to zero- cross of sync) exceeds 3.5 - 3.7 microseconds, the
message is invalidated.
3.3.4.4
RT - RT NO RESPONSE COUNTER
The no response counter checks the response time of the transmitting RT in a RT to RT transfer.
If the response time is exceeded, the message is invalidated. The response time is software
programmable (14, 18, 26, 42 microseconds) to accommodate systems with long cables and/ or
slow terminals.
3.3.4.5
MINIMUM RESPONSE TIME COUNTER
The minimum response time counter ensures that the response will be no sooner than 4
microseconds
(measured from zero- cross of parity to zero- cross of sync).
3.3.4.6
FAIL -SAFE TIMEOUT COUNTER
This counter inhibits the encoder outputs and issues a TIMEOUT interrupt whenever continuous
transmission exceeds 768/ 672 microseconds. Transmission will remain inhibited until a
command is received on the same bus or the part is reset.
3.3.5
MESSAGE PROCESSOR UNIT
The MPU forms the heart of the protocol chip and controls the operation of the Decoders,
Encoders, and Interrupt Controller. This unit is activated by the reception of a valid legal
command addressed to the RT in the RT mode and the START bit in CONFIGURATION 1 in both
the BC and MT modes.
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