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参数资料
| 型号： | NHI-1598ET/883 |
| 厂商： | NATIONAL HYBRID INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封装： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件页数： | 8/89页 |
| 文件大小： | 569K |
| 代理商： | NHI-1598ET/883 |
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15
4.2.0
INTERNAL REGISTERS
4.2.1
CONTROL
Address: 0
R/ W
BC/ MT/ RT
This register controls the general operation of the NHi- ET.
15
14
13
12
11
10
9
8
HWD
RSP1
RSP0
TSTFST
NBCST
TXINH
LOOPB
LOOPA
7
6
5
4
3
2
1
0
IRE
MIO
CMDO
SRQRST
SSF_TF
NTAG
BINH
AINH
HWD
Bits: 15
BC/ RT
1 = Enables high word detection.
This option allows extra words in a message to be detected,as required by some protocols.
0= Tterminal does not detect high word errors.
RSP1, RSP0
Bits: 14,13
BC/ RT
These bits define the response timeout for RT- RT messages in the RT mode and terminal
response timeout in the BC mode as follows:
RSP1
RSP0
TIMEOUT(us)
0
14
0
1
18
1
0
26
1
42
TSTFST
Bits: 12
RT
1= Enables testing of the FAIL SAFE time out.
When this feature is enabled, the RT will transmit continuously once it is enabled by a valid
message. The encoder will be inhibited after 768/ 672us. It will be enabled by a reset or the
reception of another valid message. If this bit is set to 0 during an RT transmission, before
the required number of words have been transmitted, the encoder will return to normal
operation and stop at the proper message length.. If it is set to 0 after the message length
has been exceeded, the current word will be completed and normal operation resumed.
This feature can be used in the LOOPBACK mode to automatically transmit data words.
The RT encoder will remain in the tester mode until the CPU sets this bit to 0.
The TSTFST Bit Must Always Be Set to Zero During Normal Operation!!!
NBCST
Bits: 11
RT
1= Specifies that broadcast commands WILL be ignored by the RT.
TXINH
Bits: 10
BC/ RT
1= Inhibits transmission by forcing TXA= TXAN= 0 and TXB= TXBN= 0.
LOOPA( B)
Bits: 9, 8
RT
1= Defines that decoder A (B) inputs shall be connected internally to the encoder outputs rather
than the transceiver for test purposes.
IRE
Bits: 7
BC/ MT/ RT
1= Globally enables the interrupt request output, *IRQ.
0= Disables all interrupt requests; however, interrupt vectors are still pushed onto the FIFO.
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