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参数资料
| 型号： | NHI-1598ET/883 |
| 厂商： | NATIONAL HYBRID INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封装： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件页数： | 2/89页 |
| 文件大小： | 569K |
| 代理商： | NHI-1598ET/883 |
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9
3.2.0
BLOCK DIAGRAM
The NHi- ETs contains two +5 volt transceivers, an ASIC, and an SRAM. The ASIC performs all
multi protocol functions; BUS CONTROLLER, BUS MONITOR and REMOTE TERMINAL. It
controls accesses to the RAM such that it appears to the host CPU 16bit wide dual port memory.
Since the NHi- ET appears to its host as RAM, no external logic is required when interfacing to
the device. It is simply connected to the CPU's address bus, Mil Bus, and control lines. There are
NO EPROMS required to illegalize commands in the RT mode. Illegalization is performed internal
to the protocol chip in the NHi- ET.The user sets up command illegalization when the NHi- ET is
initialized. See sections on Message Illegalization and Host Initialization.
NHi-ET ENHANCED TERMINAL FUNCTIONAL BLOCK DIAGRAM
The NHi- ET can be interfaced to an 8 bit CPU Bus by folding the upper and lower bytes on top of
each other and performing byte wide data transfers.
By default, the host has priority in accessing the I/ O bus. When the host requests access to a
device already in use by the protocol chip, the host *DTACK signal is delayed by the NHi- ET. If
either side (protocol chip or host) waits for access during the current cycle, it is automatically
granted priority for the next cycle. The host can retain priority for successive cycles accessing the
same address (this is required to guarantee the proper operation of host read- modify- write
instructions - see pin *HCS for details) by keeping *HCS low.
TRANSCEIVER
CHANNELA
TRANSCEIVER
CHANNELB
PROTOCOL
BUSCONTROLLER
REMOTETERMINAL
BUSMONITOR
SRAM
BUS_A
BUS_A_L
TXINH_A
BUS_B
BUS_B_L
TXINH_B
CS_L
RD_L
WR_L
ADDR
DATA
CMDS
MDCDRST
PLSCMD/BUS_JAM
SSF_TF
H_DAT(15:0)
H_ADR(16/14:1)
HCS_L
HRD_L
HWRH_L
HWRL_L
DTACK_L
IRQ_L
INTACK_L
DSC_INTPO_L
INTPI_L
MRST_L
CLK
I/O_WR_L
I/O_RD_L
I/O_ADR(2:1)
I/O_DAT(7:0)
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