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参数资料
| 型号： | NHI-1598ET/883 |
| 厂商： | NATIONAL HYBRID INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封装： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件页数： | 17/89页 |
| 文件大小： | 569K |
| 代理商： | NHI-1598ET/883 |
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4.2.14
LAST STATUS REGISTER
Address: 12
R
RT
This register holds the Status Word assosciated with the last message. After initialization of the
RT, the BUSY bit= 1, the TADR field contains the hardwire address, and all other bits are set to
0.
See RTC CONTROL REGISTER for special options.
4.2.15
RESET REMOTE TERMINAL
Address: 15
W
BC/ MT/ RT
Writing a word to address 15 resets the RT and causes it to perform its initialization (see
initialization section).
4.2.16
ENCODER STATUS
Address: 18
R
BC/ RT
This register contains flags indicating the status of the encoder. These flags are intended to
facilitate transmission of messages in loop- back mode during self- test.
15
7
0
TXREQ_L
EOTX_L
FAILSAFE_L
TXREQ_ L
Bits: 15
RT
0= Indicates that the encoder is ready to accept the next word for transmission. This bit should
equal "0" before loading the Encoder Data register with the next word. In order to transmit
contiguous words, the next word should be loaded within 18 microseconds after *TXREQ
transitions to "0".
EOTX_ L
Bits: 7
RT
0= Indicates that the encoder has completed transmission and that there are no pending
requests.
FAILSAFE_ L
Bits: 0
BC/ RT
0= FAILSAFE TIME OUT has occurred. This bit will be set to a "1" when a new message is
received or during a reset.
4.2.17
CONDITION REGISTER
Address: 19
R
BC/ MT/ RT
This register contains information about the command being processed by the NHi- ET. and the
operational condition.of the NHi-ET.
15
14
13
12
11
10
9
8
X
AXEN
BXEN
TFE
X
MDCD_L
X
7
6
5
4
3
2
1
0
X
CUFRM
BUSY
EOF B
EOF A
CUR
FRM
CUR
BUS
BUSJAM
B
BUSJAM
A
AXEN
Bits: 13
BC/ RT
1= Indicates that transmitter A is enabled. This bit is set to a "1": at POWER UP, if the NHi- ET is
RESET, after receipt of a "Reset" mode code, or after receipt of an OVERRIDE
TRANSMITTER SHUTDOWN mode code on the B bus.
0= Indicates that transmitter A is inhibited. This bit is set to a "0" after receipt of TRANSMITTER
SHUTDOWN mode code on the B bus.
BXEN
Bits: 12
BC/ RT
1= Indicates that transmitter B is enabled. This bit is set to a "1": at POWER UP, if the NHi- ET is
RESET, after receipt of a "Reset" mode code, or after receipt of an OVERRIDE
TRANSMITTER SHUTDOWN mode code on the A bus.
0= Indicates that transmitter B is inhibited. This bit is set to a "0" after receipt of a
TRANSMITTER SHUTDOWN mode code on the A bus.
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