参数资料
型号: NOIL1SE3000A-GDC
厂商: ON Semiconductor
文件页数: 10/57页
文件大小: 0K
描述: IC IMAGE SENSOR 3MP 369-PGA
标准包装: 1
系列: *
象素大小: 8µm x 8µm
有源象素阵列: 1696H x 1710V
每秒帧数: 485
电源电压: 2.5V, 3.3V
类型: CMOS 成像
封装/外壳: *
供应商设备封装: *
包装: *
其它名称: CYIL1SE3000AA-GZDC
CYIL1SE3000AA-GZDC-ND
NOIL1SN3000A
Figure 10. Analog Frontend and ADC Concept
Table 9. PROGRAMMABLE AMPLIFIERS GAIN SETTIN GS
Register Address d73
Gain Level
Comments
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
x
1x
1.5x
2.0x
2.25x
3.0x
4.0x
3.0x
POR default value
Do not use (Redundant gain codes)
The gain is set through bits 2:0 in register 73 (decimal).
The gain register controls the gain setting globally for all
64 PGA and ADC channels.
A latency (delay) is incurred for the analog signal
processing, PGA, and ADC stages. The total latency is 44
high-speed input clock delays. The output synchronization
signals from the LVDS sync channel factor in this latency.
Programmable Dark Level
An SPI-controlled DAC provides the PGA with a dark
level. This analog voltage corresponds with the all-zero
output of the ADC. This dark level is tuned to optimally use
the ADC range.
The dark level coming from the pixels follow a Gaussian
distribution. This distribution is visible in a dark image as
the FPN. The spread on the distribution is influenced by the
dark current and temperature. Typically the spread is
100 mV peak-to-peak.
The average dark level of this distribution depends on
several parameters:
? The processing corner
? Tolerances on the pixel power supplies (Vpix, Vreset,
Vmem_l, and Vmem_h)
? Pixel timing
The combination of these parameters adds an offset to the
To allow off-chip FPN calibration, the full spread on the
dark level is mapped inside the range of the ADC. To
optimally use the input range of the ADC, the spread on the
dark level is mapped as close as possible to the high level of
the ADC’s input range.
The default startup value of the dark level coming from the
DAC is 1.5 V. This ensures that the spread on the dark level
is completely mapped in the ADC range. The startup DAC
dark level is not optimal. By taking a dark image after
startup, the offset on the dark image histogram is measured.
The offset from the optimal case is subtracted from the dark
level coming from the DAC. This places the dark level
distribution optimally inside the range of the ADC. Follow
this procedure after every change in operation condition
such as temperature, FOT timing, and ROT.
Analog- to-Digital Converters
LUPA3000 includes 64 pipelined 9-bit ADCs operating at
approximately 25.75 mega samples per second (MSPS).
Two ADCs are combined to provide digitized data to one of
the 32 LVDS serialization channels. One of the ADC pair
converts data from an ‘odd kernel’ of the LUPA3000 pixel
array, the other from an ‘even kernel’. LUPA3000 only
processes the eight MSBs of the converter to realize an
improved noise performance 8-bit converter.
dark level. The offset is in the order of magnitude of 200 mV.
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