参数资料
型号: NOIL1SE3000A-GDC
厂商: ON Semiconductor
文件页数: 36/57页
文件大小: 0K
描述: IC IMAGE SENSOR 3MP 369-PGA
标准包装: 1
系列: *
象素大小: 8µm x 8µm
有源象素阵列: 1696H x 1710V
每秒帧数: 485
电源电压: 2.5V, 3.3V
类型: CMOS 成像
封装/外壳: *
供应商设备封装: *
包装: *
其它名称: CYIL1SE3000AA-GZDC
CYIL1SE3000AA-GZDC-ND
NOIL1SN3000A
Image Format and Readout Protocol
The active area read out by the sequencer in full frame
mode is shown in Figure 24. Pixels are always read in
multiples of 32.
Integration Timing
The integration time is controlled through the
EXPOSURE_1 pin. The rising edge of EXPOSURE
determines the start of exposure and the falling edge of
EXPOSURE_1 starts the FOT and determines the end of the
integration time.
The falling edge of the internal pixel reset pulse causes a
visible crosstalk in the image, unless the edge occurs in the
beginning of the ROT during readout. As a result, the
EXPOSURE pulse is internally delayed until the next ROT.
The duration of this delay depends on the length of the line
being readout. If the EXPOSURE_1 is after Lx is finished,
then integration starts immediately. There is no need to wait
for ROT.
The internal timing of the FOT is controlled by the
32 pixels
Timeslot 1
32 pixels
Timeslot 53
sequencer. The length of the FOT is set by the SPI registers
PRECHARGE_TIMER, SAMPLE_TIMER,
VMEM_TIMER, and FOT_TIMER.
Figure 24. Sensor Read Out Format
Sensor Timing and Readout
High Level Timing
The LUPA3000 sensor is a pipelined synchronous shutter.
This indicates that light integration and readout occur in
parallel, achieving the high frame rate and data throughput.
The maximum frame rate of the sensor is determined by
the time needed to readout a full frame. This frame time is
separated in the FOT and the time to readout all lines. The
readout of a line is separated in a ROT and the readout of all
kernels.
Integration frame I+1
Readout frame I
Readout Lines
Ensure that pixel_reset is high for at least 3 m s.
FOT Starts After Readout
This is the normal situation where a full window is
readout. A full window refers to the resolution set by the
Y_START, Y_END, and NB_OF_KERNELS register. This
may be the full resolution or a partial window. Figure 26
shows a high level timing; ‘Lx’ refers to ‘line x’.
When EXPOSURE_1 goes low, the FOT begins
immediately. Integration time continues until the falling
edge of pix_sample. The falling edge of pix_sample is a
fixed amount of time after the falling edge of
EXPOSURE_1. This time is set SAMPLE_TIMER (see
Frame Overhead Time).
Integration frame I+2
Readout frame I+1
FOT
L1
L2
___
L1710
Readout Pixels
ROT
K1
K2
___
K53
Figure 25. Pipelined Operation
pix_vmem
FOT
FOT
DATA
L1
L2
L3
L x
EXPOSURE_1
wait till ROT
pix_reset
SAMPLE_TIMER
integration time
pix_sample
Figure 26. High Level Readout Timing
http://onsemi.com
36
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