参数资料
型号: NOIL1SE3000A-GDC
厂商: ON Semiconductor
文件页数: 29/57页
文件大小: 0K
描述: IC IMAGE SENSOR 3MP 369-PGA
标准包装: 1
系列: *
象素大小: 8µm x 8µm
有源象素阵列: 1696H x 1710V
每秒帧数: 485
电源电压: 2.5V, 3.3V
类型: CMOS 成像
封装/外壳: *
供应商设备封装: *
包装: *
其它名称: CYIL1SE3000AA-GZDC
CYIL1SE3000AA-GZDC-ND
NOIL1SN3000A
LVDS Output Current Adjust Register (b1001000 / d72)
The LVDS output drive current is adjusted with this
control register. The startup value is b0110 that represents
3.76 mA, reflecting the typical LVDS operating point. There
Table 44. MISC2 SUPERBLK CONTROL REGISTER
Value Effect
bg_disable, bit <0>
are 16 programmable values available. For more
information, see the section LVDS Data Channels on
page 13.
Programmable Gain Register (b1001001 / d73)
The amount of analog gain (in the AFE) is adjusted from
1x–4x in eight steps. This is used with the vref_trim register
to match the ADC dynamic range to the pixel voltage range.
The startup value for this register is b000, which
corresponds to a unity gain (1x). See Programmable Gain
Amplifiers (PGA) on page 9 for information on the control
bit to gain setting table relationship.
Misc2 SuperBlk Control Register (b1001010 / d74)
The misc2 superblk control register contains additional
analog bias and reference controls. The bits are defined in
this section.
? bg_disable, bit <0>: This bit is provided if the on-chip
bandgap needs to be disabled.
? int_res, bit<1>: This bit controls whether an on-chip or
external resister is used in setting the bandgap voltage.
? pwd_bg, bit<2>: This bit is provided to power down the
bandgap. It is intended for test and debug only .
? pwd_vdark, bit<3>: This bit is provided to power down
the driver for the dark reference voltage. It is intended
for test and debug only.
? pwd_vref, bit<4>: This bit is provided to power down
the voltage references, vrefp and vrefm. It is intended
for test and debug only.
? pwd_vcm, bit<5>: This bit is fixed to ‘1’. See Table 44.
? sblk_spare3, bit<6>: This bit is a spare control bit. It is
set to ‘0’ at POR.
? sblk_spare4, bit<7>: This bit is a spare control bit. It is
set to ‘1’ at POR.
0
1
On startup
int_res, bit<1>
0
1
On startup
pwd_bg, bit<2>
0
1
On startup
pwd_vdark, bit<3>
0
1
On startup
pwd_vref, bit<4>
0
1
On startup
pwd_vcm, bit<5>
1
On startup
sblk_spare3, bit<6>
0
1
On startup
sblk_spare4, bit<7>
0
1
On startup
On-chip bandgap enabled
Normal operation
On-chip bandgap disabled
0
External resistor used in Normal operation
On-chip resister used
0
Normal operation
Bandgap powered down
0
Normal operation
Power down vdark buffer
0
Normal operation
Power down vrefp/vrefm references
0
Disable on-chip VCM generation. Apply
0.9 V to Vcm pin 87 and decouple to
ground with 10 nF capacitor.
1
Normal operation
0
Normal operation
1
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