参数资料
型号: NOIV1SE025KA-GDC
厂商: ON Semiconductor
文件页数: 5/76页
文件大小: 0K
描述: IC IMAGE SENSOR 25MP 355PGA
标准包装: 14
系列: *
象素大小: 4.5µm x 4.5µm
有源象素阵列: 5120H x 5120V
每秒帧数: 53
类型: CMOS 成像
封装/外壳: *
供应商设备封装: *
包装: *
NOIV1SN025KA
Electrical Specifications
Power Supply Ratings
Table 5. POWER SUPPLY RATINGS
Limits in bold apply for for T J = T MIN to T MAX , all other limits T J = +30 ° C [5], [6], [7], [8]
Parameter
Description
Min
Typ
Max
Units
Power Supply Parameters
vdda_33
Idda_33
vddd_33
Iddd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
vdd_resfd
gnd_resfd
vdd_respd
gnd_respd
vdd_trans
gnd_trans
vdd_sel
gnd_sel
vdd_casc
vref_colmux [8]
gnd_colbias
gnd_colpc
Ptot
Pstby
Analog supply - 3.3 V domain. gnda_33 is connected to substrate
Current consumption from analog supply
Digital supply - 3.3 V domain. gndd_33 is connected to substrate
Current consumption from 3.3 V digital supply
Digital supply - 1.8 V domain. gndd_18 is connected to substrate
Current consumption 1.8 V digital supply
Pixel array supply
Current consumption from pixel supply
Floating diffusion reset supply
Floating diffusion reset ground. Not connected to substrate
Photo diode reset supply
Photo diode reset ground. Not connected to substrate.
Note This is a sinking power supply with 200 mA range.
Pixel transfer supply
Pixel transfer ground. Not connected to substrate
Pixel select supply
Pixel select ground. Not connected to substrate.
Cascode supply
Column multiplexer reference supply
Column biasing ground. Dedicated ground signal for pixel biasing.
Connected to substrate
Column precharge ground. Dedicated ground signal for pixel bias-
ing. Not connected to substrate
Total power consumption
Power consumption in standby mode
3
675
3
65
1.6
240
3
25
3.3
0
3.3
0
3.3
0
3.0
0
0.9
3000
3.3
725
3.3
85
1.8
310
3.3
35
4.5
0
4.2
0
4.2
0
3.3
0
1.0
1.0
0
0
3400
3.6
775
3.6
105
2
380
3.6
45
4.6
1.0
4.6
1.0
4.6
1.0
3.6
0
1.1
3800
50
V
mA
V
mA
V
mA
V
mA
V
V
V
V
V
V
V
V
V
V
V
V
mW
mW
Popt
Power consumption at lower pixel rates
Configurable
I/O - LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels in 10-bit mode
620
Mbps
DDR signaling - 32 data channels, 1 synchronization channel
fserdata
Data rate on data channels in 8-bit mode
496
Mbps
DDR signaling - 32 data channels, 1 synchronization channel
fserclock
fserclock
Clock rate of output clock in 10-bit mode
Clock output for mesochronous signaling
Clock rate of output clock in 8-bit mode
Clock output for mesochronous signaling
310
248
MHz
MHz
Vicm
Tccsk
LVDS input common mode level
Channel to channel skew (training pattern allows per-channel skew
correction)
0.3
1.25
2.2
50
V
ps
LVDS Electrical/Interface
fin
fin
Input clock rate for 10-bit mode
Input clock rate for 8-bit mode
310
248
MHz
MHz
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