- 您现在的位置：买卖IC网 > PDF目录189259 > NT2GT72U4PD0BV-3C (NANYA TECHNOLOGY CORP) 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 PDF资料下载
参数资料
| 型号： | NT2GT72U4PD0BV-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 10/27页 |
| 文件大小： | 648K |
| 代理商： | NT2GT72U4PD0BV-3C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
REV 1.1
18
01/2009
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V) [1GB, 1Rank, 128Mx8 DDR2 SDRAMs]
Symbol
Parameter/Condition
PC2-5300
(-3C)
PC2-6400
(-AD)
Unit
I DD0
Operating Current: One bank Active – Precharge; tCK = tCK (MIN), tRC = tRC (MIN), tRAS = tRAS (MIN), CKE is
HIGH,
is HIGH between valid commands. Address and control inputs are switching; Data bus
inputs are switching.
1243
1392
mA
I DD1
Operating Current: One bank; active/read/precharge; BL = 4; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT
= 0mA; tRAS = tRAS (MIN). CKE is HIGH,
is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
1144
1293
mA
I DD2P Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are
floating.
332
mA
I DD2N Precharge Standby Current: All banks idle;
is HIGH; CKE is HIGH. tCK = tCK (MIN). Other control
and address inputs are switching, data bus inputs are switching.
897
997
mA
I DD2Q Precharge Quiet Standby Current: All banks idle;
is HIGH; CKE is HIGH; tCK = tCK (MIN); Other
control and address inputs are stable, Data bus inputs are floating.
748
798
mA
I DD3PF
Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast
Power-down Exit).
530
550
mA
I DD3PS
Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow
Power-down Exit).
362
mA
I DD3N
Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CLMIN; tRAS =
tRAS (MAX); tRP = tRP (MIN); tCK = tCK (MIN); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data bus inputs are switching; I OUT = 0mA
847
946
mA
I DD4R
Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL MIN;
tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MIN); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data bus inputs are switching.
1441
1590
mA
I DD4W
Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL
MIN; tCK = tCK (MIN); tRAS = tRAS (MAX);
tRP = tRP (MAX); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data bus inputs are switching.
1293
1441
mA
I DD5
Auto-Refresh Current: tRC = tRFC (MIN), Refresh command every tRFC = tRFC (MIN) interval, CKE is HIGH,
CS is HIGH between valid commands, other control and address inputs are switching, Data bus
inputs are switching.
1837
1986
mA
I DD6
Self-Refresh Current: CKE
≤ 0.2V; external clock off, CK and
at 0V; Other control and address
inputs are floating, Data bus inputs are floating. RESET is LOW. IDD6 current values are guaranteed
up to TCASE of 85 C max
342
mA
I DD7
All Bank Interleave Read Current: All banks are being interleaved at minimum tRC without violating
tRRD using a burst length of 4. Control and address bus inputs are stable during deselects. IOUT =
0mA
2085
2283
mA
Note: Module IDD was calculated from component IDD. It may different from the actual measurement.
相关PDF资料 |
PDF描述 |
|---|---|
| NT512T64U88B0BY-3C | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| NT56V6620C0T-75 | SYNCHRONOUS DRAM, PDSO54 |
| NT5CB256M4AN-BF | DDR DRAM, PBGA78 |
| NT5DS64M8BF-6KI | DDR DRAM, PBGA60 |
| NT5SE8M16DS-6K | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT2H0301F0DTL,125 | 功能描述:RFID应答器 RoHS:否 制造商:NXP Semiconductors 存储容量: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Reel |
| NT2H0301F0DTP,118 | 制造商:NXP Semiconductors 功能描述:NT2H0301F0DTP - Tape and Reel 制造商:NXP Semiconductors 功能描述:PHANT2H0301F0DTP,118 NFC FORUM TYPE 2 TA 制造商:NXP Semiconductors 功能描述:IC SMART TAG NFC TYPE 2 8HWSON 制造商:NXP Semiconductors 功能描述:NT2H0301F0DTP/HWSON8/REEL13// |
| NT2H0301F0DTP,147 | 制造商:NXP Semiconductors 功能描述:CHIPSET |
| NT2H0301F0DUDV | 制造商:NXP Semiconductors 功能描述:CHIPSET |
| NT2H0301G0DUD,005 | 制造商:NXP Semiconductors 功能描述:NT2H0301G0DUD/UNCASED/FOIL// - Gel-pak, waffle pack, wafer, diced wafer on film 制造商:NXP Semiconductors 功能描述:IC SMART TAG NFC TYPE 2 UNCASED |
发布紧急采购，3分钟左右您将得到回复。