![](http://datasheet.mmic.net.cn/170000/NT2GT72U4PD0BV-3C_datasheet_9570972/NT2GT72U4PD0BV-3C_20.png)
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
REV 1.1
20
01/2009
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V) [2GB, 2Rank, 128Mx8 DDR2 SDRAMs]
Symbol
Parameter/Condition
PC2-5300
(-3C)
PC2-6400
(-AD)
Unit
I DD0
Operating Current: One bank Active – Precharge; tCK = tCK (MIN), tRC = tRC (MIN), tRAS = tRAS (MIN), CKE is
HIGH,
is HIGH between valid commands. Address and control inputs are switching; Data bus
inputs are switching.
1925
2173
mA
I DD1
Operating Current: One bank; active/read/precharge; BL = 4; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT
= 0mA; tRAS = tRAS (MIN). CKE is HIGH,
is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
1826
2074
mA
I DD2P Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are
floating.
499
mA
I DD2N Precharge Standby Current: All banks idle;
is HIGH; CKE is HIGH. tCK = tCK (MIN). Other control
and address inputs are switching, data bus inputs are switching.
1628
1829
mA
I DD2Q Precharge Quiet Standby Current: All banks idle;
is HIGH; CKE is HIGH; tCK = tCK (MIN); Other
control and address inputs are stable, Data bus inputs are floating.
1331
1430
mA
I DD3PF
Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast
Power-down Exit).
895
935
mA
I DD3PS
Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow
Power-down Exit).
559
mA
I DD3N
Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CLMIN; tRAS =
tRAS (MAX); tRP = tRP (MIN); tCK = tCK (MIN); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data bus inputs are switching; I OUT = 0mA
1529
1727
mA
I DD4R
Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL MIN;
tCK = tCK (MIN); tRAS = tRAS (MAX); tRP = tRP (MIN); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data bus inputs are switching.
2123
2371
mA
I DD4W
Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL
MIN; tCK = tCK (MIN); tRAS = tRAS (MAX);
tRP = tRP (MAX); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data bus inputs are switching.
1975
2222
mA
I DD5
Auto-Refresh Current: tRC = tRFC (MIN), Refresh command every tRFC = tRFC (MIN) interval, CKE is HIGH,
CS is HIGH between valid commands, other control and address inputs are switching, Data bus
inputs are switching.
2519
2767
mA
I DD6
Self-Refresh Current: CKE
≤ 0.2V; external clock off, CK and
at 0V; Other control and address
inputs are floating, Data bus inputs are floating. RESET is LOW. IDD6 current values are guaranteed
up to TCASE of 85 C max
519
mA
I DD7
All Bank Interleave Read Current: All banks are being interleaved at minimum tRC without violating
tRRD using a burst length of 4. Control and address bus inputs are stable during deselects. IOUT =
0mA
2767
3064
mA
Note: Module IDD was calculated from component IDD. It may different from the actual measurement.