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参数资料
| 型号： | NT512T64U88B0BY-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 1/24页 |
| 文件大小： | 473K |
| 代理商： | NT512T64U88B0BY-3C |
NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2
1
03/2007
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
240pin Unbuffered DDR2 SDRAM MODULE
Based on 64Mx8 & 32Mx16 DDR2 SDRAM B Die
Features
Performance:
PC2-4200
PC2-5300
PC2-6400
Speed Sort
-37B
-3C
-25D
-25C
DIMM
Latency*
4
5
6
5
Unit
f CK Clock Frequency
266
333
400
MHz
t CK Clock Cycle
3.75
3
2.5
ns
f DQ DQ Burst Frequency
533
667
800
MHz
JEDEC Standard 240-pin Dual In-Line Memory Module
32Mx64 DDR2 Unbuffered DIMM based on 32Mx16 DDR2
SDRAM
(NT5TU32M16BG)
64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on
64Mx8 DDR2 SDRAM
(NT5TU64M8BE)
Intended for 266MHz, 333MHz, and 400MHz applications
Inputs and outputs are SSTL-18 compatible
VDD = VDDQ = 1.8Volt ± 0.1
SDRAMs have 4 internal banks for concurrent operation
Differential clock inputs
Data is read or written on both clock edges
Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
Address and control signals are fully synchronous to positive
clock edge
Programmable Operation:
- Device
Latency: 4, 5, 6
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
Auto Refresh (CBR) and Self Refresh Modes
Automatic and controlled precharge commands
13/10/1 Addressing (row/column/rank) – 256MB
14/10/1 Addressing (row/column/rank) – 512MB
14/10/2 Addressing (row/column/rank) – 1GB
7.8 s Max. Average Periodic Refresh Interval
Serial Presence Detect
Gold contacts
SDRAMs in 60 and 84 ball FBGA Package
RoHS compliance
Description
NT256T64UH4B0FY, NT512T64U88B0BY, and NT1GT64U8HB0BY are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM
Unbuffered Dual In-Line Memory Module (UDIMM), organized as one-rank 32Mx64 and 64Mx64 and two ranks 128Mx64 high-speed
memory array. NT256T64UH4B0FY use four 32Mx16 DDR2 SDRAMs. NT512T64U88B0BY use eight 64Mx8 DDR2 SDRAMs.
NT1GT64U8HB0BY use sixteen 64Mx8 DDR2 SDRAMs. These DIMMs are manufactured using raw cards developed for broad industry
use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2
SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 233 MHz (333MHz and 400MHz) clock speeds and achieves high-speed
data transfer rates of up to 533MHz (667MHz and 800MHz). Prior to any access operation, the device
latency and burst / length /
operation type must be programmed into the DIMM by address inputs A0-A14 and I/O inputs BA0 and BA1 using the mode register set
cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
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