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参数资料
| 型号： | NT512T64U88B0BY-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 23/24页 |
| 文件大小： | 473K |
| 代理商： | NT512T64U88B0BY-3C |
NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2
8
03/2007
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2 (256MB)
32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Byte
Description
-37B
-3C
-25D
-25C
-37B
-3C
-25D
-25C
Note
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
DDR2
08
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank, Package, and Height
1 rank, Height=30mm
60
6
Data Width of this Assembly
64
40
7
Reserved
Undefined
00
8
Voltage Interface Level of this Assembly
SSTL_1.8V
05
9
DDR2 SDRAM Device Cycle Time at CL=5
3.75ns
3ns
2.5ns
3D
30
25
10
DDR2 SDRAM Device Access Time from Clock at CL=5
±0.5ns ±0.45ns
±0.4ns
50
45
40
11
DIMM Configuration Type
Non parity/ECC
00
12
Refresh Rate/Type
7.8:s/self
82
13
Primary DDR2 SDRAM Width
x16
10
14
Error Checking DDR2 SDRAM Device Width
N/A
00
15
Reserved
Undefined
00
16
DDR2 SDRAM Device Attributes: Burst Length Supported
4,8
0C
17
DDR2 SDRAM Device Attributes: Number of Device Banks
4
04
18
DDR2 SDRAM Device Attributes:
Latencies Supported
3,4,5
4,5,6
3,4,5
38
70
38
19
Reserved
<4.1mm
01
20
DDR2 SDRAM DIMM Type Information
Regular UDIMM (133.35mm)
02
21
DDR2 SDRAM Module Attributes:
Normal DIMM
00
22
DDR2 SDRAM Device Attributes: General
Support weak Driver,
50; ODT, and PASR
07
23
Minimum Clock Cycle at CL=4
3.75ns
3ns
3.75ns
3D
30
3D
24
Maximum Data Access Time (tac) from Clock at CL=4
±0.5ns
±0.45ns ±0.5ns
50
45
50
25
Minimum Clock Cycle Time at CL=3
5.0ns
3.75ns
5.0ns
50
3D
50
26
Maximum Data Access Time (tac) from Clock at CL=3
0.6ns
0.5ns
0.6ns
60
50
60
27
Minimum Row Precharge Time (tRP)
15.0ns
12.0ns
3C
32
28
Minimum Row Active to Row Active delay (tRRD)
10ns
28
29
Minimum RAS to CAS delay (tRCD)
15.0ns
12.0ns
3C
32
30
Minimum RAS Pulse Width (tRAS)
45.0
2D
31
Module Bank Density
256MB
40
32
Address and Command Setup Time Before Clock (tIS)
0.25ns
0.20ns
0.175ns
25
20
17
33
Address and Command Hold Time After Clock (tIH)
0.375ns 0.275ns
0.25ns
37
27
25
34
Data Input Setup Time Before Clock (tDS)
0.10ns
0.05ns
10
05
35
Data Input Hold Time After Clock (tDH)
0.225ns 0.175ns
0.125ns
22
17
12
36
Write Recovery Time (tWR)
15.0ns
3C
37
Internal Write to Read Command delay (tWTR)
7.5ns
1E
38
Internal Read to Precharge delay (tRTP)
7.5ns
1E
39
Memory Analysis Probe Characteristics
Undefined
00
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