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参数资料
| 型号： | NT5SE8M16DS-6K |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封装： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件页数： | 1/64页 |
| 文件大小： | 1153K |
| 代理商： | NT5SE8M16DS-6K |
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NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
1
REV 1.0
May 9, 2005
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Features
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BA0/BA1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8 or full page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
Random Column Address every CK (1-N Rule)
Single Power Supply, either 3.3V or 2.5V
LVTTL compatible
Packages: TSOP-Type II
Lead-free & Halogen-free product available
Description
The NT5SV8M16DS, NT5SV8M16DT, NT5SE8M16DS and
NT5EV8M16DT are four-bank Synchronous DRAMs orga-
nized as 2Mbit x 16 I/O x 4 Bank. These synchronous
devices achieve high-speed data transfer rates of up to
166MHz by employing a pipeline chip architecture that syn-
chronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve addresses (A0-A11) and two bank
select addresses (BA0, BA1) are strobed with RAS. Nine col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
Maximum Operating Speed
CAS
Latency
PC166
(6K)
PC133
(75B)
2
10
ns
3
67.5
ns
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相关代理商/技术参数 |
参数描述 |
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| NT5SV16M16AT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75BL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
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