NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
38
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock and Clock Enable Parameters
Symbol
Parameter
-6K
-75B
Units Notes
Min.
Max.
Min.
Max.
tCK3
Clock Cycle Time, CAS Latency = 3
6.0
1000
7.5
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
7.5
—
10
—
ns
tAC3 (A)
Clock Access Time, CAS Latency = 3
—
ns
tAC2 (A)
Clock Access Time, CAS Latency = 2
—
ns
tAC3 (B)
Clock Access Time, CAS Latency = 3
—
5
—
5.4
ns
tAC2 (B)
Clock Access Time, CAS Latency = 2
—
5.4
—
6
ns
tCKH
Clock High Pulse Width
2
—
2.5
—
ns
tCKL
Clock Low Pulse Width
2
—
2.5
—
ns
tCES
Clock Enable Set-up Time
1.5
—
1.5
—
ns
tCEH
Clock Enable Hold Time
0.8
—
0.8
—
ns
tSB
Power down mode Entry Time
0
6
0
7.5
ns
tT
Transition Time (Rise and Fall)
0.3
8
0.5
10
ns
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
Symbol
Parameter
-6K
-75B
Units Notes
Min.
Max.
Min.
Max.
tCS
Command Setup Time
1.5
—
1.5
—
ns
tCH
Command Hold Time
0.8
—
0.8
—
ns
tAS
Address and Bank Select Set-up Time
1.5
—
1.5
—
ns
tAH
Address and Bank Select Hold Time
0.8
—
0.8
—
ns
tRCD
RAS to CAS Delay
16
—
20
—
ns
tRC
Bank Cycle Time
54
—
67.5
—
ns
tRAS
Active Command Period
36
100K
45
100K
ns
tRP
Precharge Time
16
—
20
—
ns
tRRD
Bank to Bank Delay Time
12
—
15
—
ns
tCCD
CAS to CAS Delay Time
1—1—
CK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
Parameter
-6K
-75B
Units
Min.
Max.
Min.
Max.
tRSC
Mode Register Set Cycle Time
12
—
15
—
ns