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参数资料
| 型号： | NT5SE8M16DS-6K |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封装： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件页数： | 2/64页 |
| 文件大小： | 1153K |
| 代理商： | NT5SE8M16DS-6K |
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NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
10
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low
at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine
whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the start-
ing column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write
operation on successive clock cycles up to 133 MHz for PC133 or upto 166MHz for PC166 devices. The number of serial data
bits for each access is equal to the burst length, which is programmed into the Mode Register.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected
row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank.
A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock
cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Com-
mand, the remaining addresses are overridden by the new address.
Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again.
To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Acti-
vate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations
are possible. By using the programmed burst length and alternating the access and precharge operations between multiple
banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are acti-
vated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be
issued to the same bank or between active banks on every clock cycle.
相关PDF资料 |
PDF描述 |
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| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
| NTC1120-12.8MHZ | Analog IC |
| NTC1120-20MHZ | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV16M16AT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75BL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
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