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参数资料
| 型号： | NT5SE8M16DS-6K |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封装： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件页数： | 24/64页 |
| 文件大小： | 1153K |
| 代理商： | NT5SE8M16DS-6K |
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NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
30
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Enable (CKE) Truth Table
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA0,
BA1
A11 - A0
Self Refresh
H
X
XXXX
X
INVALID
L
H
X
Exit Self Refresh with Device Deselect
L
H
L
H
X
Exit Self Refresh with No Operation
L
H
L
H
L
X
ILLEGAL
L
H
L
H
L
X
ILLEGAL
L
H
L
X
ILLEGAL
L
XXXX
X
Maintain Self Refresh
Power Down
H
X
XXXX
X
INVALID
L
H
X
Power Down mode exit, all banks idle
L
H
L
XXX
X
ILLEGAL
L
XXXX
X
Maintain Power Down Mode
All Banks Idle
H
XXX
Refer to the Idle State section of the
Current State Truth Table
HH
L
H
X
HH
L
H
X
H
LLL
H
X
CBR Refresh
H
LLLL
OP Code
Mode Register Set
H
L
H
XXX
Refer to the Idle State section of the
Current State Truth Table
HL
L
H
X
HL
L
H
X
H
L
H
X
Entry Self Refresh
H
L
LLLL
OP Code
Mode Register Set
L
X
XXXX
X
Power Down
Any State
other than
listed above
H
XXXX
X
Refer to operations in the Current State
Truth Table
H
L
XXXX
X
Begin Clock Suspend next cycle
L
H
XXXX
X
Exit Clock Suspend next cycle
L
XXXX
X
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE
(tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising
clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-
tion.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
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相关代理商/技术参数 |
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| NT5SV16M16AT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
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