- 您现在的位置：买卖IC网 > PDF目录189259 > NT5SE8M16DS-6K (NANYA TECHNOLOGY CORP) 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 PDF资料下载
参数资料
| 型号： | NT5SE8M16DS-6K |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封装： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件页数： | 22/64页 |
| 文件大小： | 1153K |
| 代理商： | NT5SE8M16DS-6K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
29
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Command Truth Table (See note 1)
Function
Device State
CKE
CS
RAS
CAS
WE
DQM
BA0,
BA1
A10
, A11,
A9-A0
Notes
Previous
Cycle
Current
Cycle
Mode Register Set
Idle
H
X
L
X
OP Code
Auto (CBR) Refresh
Idle
H
L
H
X
Entry Self Refresh
Idle
H
L
H
X
Exit Self Refresh
Idle (Self-
Refresh)
LH
HX
X
XX
X
LH
H
Single Bank Precharge
See Current
State Table
HX
L
H
L
X
BS
L
X
Precharge all Banks
See Current
State Table
HX
L
H
L
X
H
X
Bank Activate
Idle
H
X
L
H
X
BS
Row Address
Write
Active
H
X
L
H
L
X
BS
L
Column
Write with Auto-Precharge
Active
H
X
L
H
L
X
BS
H
Column
Read
Active
H
X
L
H
L
H
X
BS
L
Column
Read with Auto-Precharge
Active
H
X
L
H
L
H
X
BS
H
Column
Reserved
H
X
L
H
L
X
No Operation
Any
H
X
L
H
X
Device Deselect
Any
H
X
H
X
Clock Suspend Mode Entry Active
H
L
X
Clock Suspend Mode Exit
Active
L
H
X
Data Write/Output Enable
Active
H
X
L
X
Data Mask/Output Disable
Active
H
X
H
X
Power Down Mode Entry
Idle/Active
H
L
HX
X
XX
X
LH
H
Power Down Mode Exit
Any (Power
Down)
LH
HX
X
XX
X
LH
H
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the
Current State Truth Table.
2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1
selects bank 3.
3. Not applicable.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device
state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in
this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
相关PDF资料 |
PDF描述 |
|---|---|
| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
| NTC1120-12.8MHZ | Analog IC |
| NTC1120-20MHZ | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV16M16AT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75BL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
发布紧急采购，3分钟左右您将得到回复。