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参数资料
| 型号： | NT5SE8M16DS-6K |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封装： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件页数： | 21/64页 |
| 文件大小： | 1153K |
| 代理商： | NT5SE8M16DS-6K |
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NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
28
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks
is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”
any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and
the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands
that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE
returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto
the DQ pins will be actively held valid until Clock Suspend mode is exited.
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-
pend mode is exited.
Clock Suspend during a Read Cycle
Clock Suspend during a Write Cycle
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
READ A
NOP
CKE
DQs
DOUT A0
DOUT A2
DOUT A1
: “H” or “L”
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DOUT element at the DQs when the
suspend operation starts is held valid
(Burst Length = 4, CAS Latency = 2)
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITE A
NOP
CKE
DQs
DIN A2
DIN A3
: “H” or “L”
A one clock delay before
suspend operation starts
A one clock delay to exit
the Suspend command
DIN is masked during the Clock Suspend Period
DIN A1
DIN A0
(Burst Length = 4, CAS Latency = 2)
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相关代理商/技术参数 |
参数描述 |
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| NT5SV16M16AT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-75BL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
| NT5SV16M16AT-7KL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Synchronous DRAM |
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