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参数资料
| 型号： | NT5SE8M16DS-6K |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封装： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件页数： | 25/64页 |
| 文件大小： | 1153K |
| 代理商： | NT5SE8M16DS-6K |
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NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
31
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Current State Truth Table (Part 1 of 3)(See note 1)
Current State
Command
Action
Notes
CS RAS CAS WE BA0,BA1
A11 - A0
Description
Idle
LLLL
OP Code
Mode Register Set
Set the Mode Register
L
H
X
Auto or Self Refresh
Start Auto or Self Refresh
L
H
L
BS
X
Precharge
No Operation
L
H
BS
Row Address Bank Activate
Activate the specified bank and row
L
H
L
BS
Column
Write w/o Precharge
ILLEGAL
L
H
L
H
BS
Column
Read w/o Precharge
ILLEGAL
L
H
X
No Operation
H
X
Device Deselect
No Operation or Power Down
Row Active
LLLL
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
BS
X
Precharge
L
H
BS
Row Address Bank Activate
ILLEGAL
L
H
L
BS
Column
Write
Start Write; Determine if Auto Precharge
L
H
L
H
BS
Column
Read
Start Read; Determine if Auto Precharge
L
H
X
No Operation
H
X
Device Deselect
No Operation
Read
LLLL
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
BS
X
Precharge
Terminate Burst; Start the Precharge
L
H
BS
Row Address Bank Activate
ILLEGAL
L
H
L
BS
Column
Write
Terminate Burst; Start the Write cycle
L
H
L
H
BS
Column
Read
Terminate Burst; Start a new Read cycle
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
Write
LLLL
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
BS
X
Precharge
Terminate Burst; Start the Precharge
L
H
BS
Row Address Bank Activate
ILLEGAL
L
H
L
BS
Column
Write
Terminate Burst; Start a new Write cycle
L
H
L
H
BS
Column
Read
Terminate Burst; Start the Read cycle
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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