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参数资料
| 型号： | NT512T64U88B0BY-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 9/24页 |
| 文件大小： | 473K |
| 代理商： | NT512T64U88B0BY-3C |
NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2
17
03/2007
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.8V ± 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-4200
(-37B)
PC2-5300
(-3C)
PC2-6400
(-25D)
PC2-6400
(-25C)
Unit
I DD0
Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
560
600
680
672
mA
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC
(MIN);
CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs
changing once per clock cycle
640
720
800
mA
I DD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE
≤ VIL (MAX); tCK = tCK (MIN)
56
mA
I DD2N
Idle Standby Current: CS
≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK
= tCK (MIN); address and control inputs changing once per clock cycle
320
400
408
mA
I DD2Q
Precharge Quiet Standby Current: All banks idle;
is HIGH; CKE is
HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data
bus inputs are floating.
280
320
360
mA
I DD3PF
Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to low (Fast Power-down Exit).
224
264
312
mA
I DD3PS
Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to high (Slow Power-down Exit).
72
mA
I DD3N
Active Standby Current: one bank; active/precharge; CS
≥ VIH (MIN);
CKE
≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
344
400
480
mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN)
880
1120
1200
mA
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT =
0mA
920
1120
1160
mA
I DD5
Auto-Refresh Current: tRC = tRFC (MIN)
1200
1280
1400
mA
I DD6
Self-Refresh Current: CKE
≤ 0.2V
56
mA
I DD7
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing at
every transfer; tRC = tRC (min); IOUT = 0mA.
1280
1360
mA
Note:
Module IDD was calculated from component IDD. It may differ from the actual measurement.
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