参数资料
型号: NT5SV8M8DT-7
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封装: 0.400 INCH, PLASTIC, TSOP2-54
文件页数: 10/21页
文件大小: 190K
代理商: NT5SV8M8DT-7
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
18
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Read Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tOH
Data Out Hold Time
ns
1
3
3
3
ns
2, 4
tLZ
Data Out to Low Impedance Time
0
0
ns
tHZ3
Data Out to High Impedance Time
2.7
5.4
2.7
5.4
2.7
5.4
ns
3
tHZ2
Data Out to High Impedance Time
2.7
5.4
2.7
5.4
3
6
ns
3
tDQZ
DQM Data Out Disable Latency
2
2
2
CK
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-5K, -7K, -75B).
Refresh Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tREF
Refresh Period
64
64
64
ms
1
tSREX
Self Refresh Exit Time
10
10
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Min.
Max.
Min.
Max.
Min.
Max.
tDS
Data In Set-up Time
1.5
1.5
1.5
ns
tDH
Data In Hold Time
0.8
0.8
0.8
ns
tDPL
Data input to Precharge
12
14
14
ns
tWR
Write Recovery Time
12
14
14
ns
tDAL3
Data In to Active Delay
CAS Latency = 3
5
5
5
CK
tDAL2
Data In to Active Delay
CAS Latency = 2
4
4
4
CK
tDQW
DQM Write Mask Latency
0
0
CK
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