- 您现在的位置：买卖IC网 > PDF目录189259 > NT5SV8M8DT-7 (NANYA TECHNOLOGY CORP) 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 PDF资料下载
参数资料
| 型号： | NT5SV8M8DT-7 |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 21/21页 |
| 文件大小： | 190K |
| 代理商： | NT5SV8M8DT-7 |
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
9
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Clock Enable (CKE) Truth Table
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BS0,
BS1
A11 - A0
Self Refresh
H
X
INVALID
1
L
H
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
X
Exit Self Refresh with No Operation
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Self Refresh
Power Down
H
X
INVALID
1
L
H
X
Power Down mode exit, all banks idle
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Power Down Mode
All Banks Idle
H
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
H
X
3
H
L
H
X
3
H
L
H
X
CBR Refresh
H
L
OP Code
Mode Register Set
4
H
L
H
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
H
X
3
H
L
H
X
3
H
L
H
X
Entry Self Refresh
4
H
L
OP Code
Mode Register Set
L
X
Power Down
4
Any State
other than
listed above
H
X
Refer to operations in the Current State
Truth Table
H
L
X
Begin Clock Suspend next cycle
5
L
H
X
Exit Clock Suspend next cycle
L
X
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE
(tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising
clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-
tion.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
相关PDF资料 |
PDF描述 |
|---|---|
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
| NTC1120-12.8MHZ | Analog IC |
| NTC1120-20MHZ | Analog IC |
| NTC1120-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV8M8DT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5TU32M16DG-3CI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-BE | 制造商:Nanya Technology Corporation 功能描述:DRAM |
发布紧急采购，3分钟左右您将得到回复。