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参数资料
| 型号： | NT5SV8M8DT-7 |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 19/21页 |
| 文件大小： | 190K |
| 代理商： | NT5SV8M8DT-7 |
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
7
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations
(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst
sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by
address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits
A7 - A11, BS0, and BS1.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst
sequences are supported, sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a
Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page(actual page length is dependent
on organization: x4, x8, or x16).Full page burst operation is only posible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the
device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with
single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to
read cycles. All write cycles are single write operations when this mode is selected.
Note: Page length is a function of I/O organization and column addressing.
x4 organization (CA0-CA9); Page Length = 1024 bits
x8 organization (CA0-CA8); Page Length = 512 bits
x16 organization (CA0-CA7); Page Length = 256 bits
Burst Length and Sequence
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
2
x x 0
0, 1
x x 1
1, 0
4
x 0 0
0, 1, 2, 3
x 0 1
1, 2, 3, 0
1, 0, 3, 2
x 1 0
2, 3, 0, 1
x 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full Page(Note)
n n n
Cn, Cn+1, Cn+2, .....
Not Supported
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相关代理商/技术参数 |
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| NT5SV8M8DT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5TU32M16DG-3CI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-BE | 制造商:Nanya Technology Corporation 功能描述:DRAM |
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