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参数资料
| 型号： | NT5SV8M8DT-7 |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 8/21页 |
| 文件大小： | 190K |
| 代理商： | NT5SV8M8DT-7 |
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
16
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Characteristics (T
A = 0 to +70?C, V DD = 3.3V ??0.3V)
1. An initial pause of 200
? s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point
5. Load Circuit A: AC measurements assume tT = 1.0ns.
6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point
7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Characteristics Diagrams
Output
Input
Clock
tOH
tSETUP
tHOLD
tAC
tLZ
1.4V
tT
Vtt = 1.4V
Output
50
?
50pF
Zo = 50?
AC Output Load Circuit (A)
tCKH
tCKL
Output
50pF
Zo = 50?
AC Output Load Circuit (B)
VIL
V
IH
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV8M8DT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5TU32M16DG-3CI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU32M16DG-BE | 制造商:Nanya Technology Corporation 功能描述:DRAM |
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