- 您现在的位置：买卖IC网 > PDF目录224604 > NT5TU64M16DG-3C (NANYA TECHNOLOGY CORP) 64M X 16 DDR DRAM, 0.45 ns, PBGA84 PDF资料下载
参数资料
| 型号： | NT5TU64M16DG-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | GREEN, BGA-84 |
| 文件页数： | 10/85页 |
| 文件大小： | 2622K |
| 代理商： | NT5TU64M16DG-3C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
18
REV 1.0
06 / 2010
EMRS(2) Extended Mode Register Set Programming
Address Field
Extended Mode
Register
1
PASR***
BA1 BA0
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*
A2
A1
A0
Partial Array Self Refresh
0
Full array
0
1
Half Array (BA[2:0]=000, 001, 010, &011)
0
1
0
Quarter Array (BA[2:0]=000&001)
0
1
1/8
th array (BA[2:0] = 000)
1
0
3 / 4 array (BA[2:0]=010,011,100,101,110, &111)
1
0
1
Half array (BA[2:0]=100, 101, 110, & 111)
1
0
Quarter array (BA[2:0]=110&111)
1
1/8
th array (BA[2:0]=111)
0
SRF
A7
0
Disable
1
Enable** (85C Tcase 95C)
High Temperature Self-Refresh Rate Enable
A12
0*
BA2
0*
BA0
MRS mode
0
MRS
1
EMRS(1)
BA1
0
1
0
EMRS(2)
EMRS(3):
Reserved
* The rest bits in EMRS(2) is reserved for future use and all bits in EMRS (2) except A0-A2,A7,BA0, and
BA1 must be programmed to 0 when setting EMRS (2) during initialization.
** DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0].
*** Optional. If PASR(Partial Array Self Refresh ) is enabled, data located in areas of the array beyond the
spec. location will be lost if self refresh is entered .
Extended Mode Register Set EMRS (2)
The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is
not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1,
while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be
satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using
the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.
EMRS(3) Extended Mode Register Set Programming
All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode
register during initialization.
相关PDF资料 |
PDF描述 |
|---|---|
| NTA2425E | |
| NTA2425F | |
| NTA2410-10 | |
| NTD2410F | |
| NTA2425-10 | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙铁 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 产品:Soldering Stations 类型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大温度:+ 850 F 电缆类型:US Cord Included |
发布紧急采购，3分钟左右您将得到回复。