- 您现在的位置：买卖IC网 > PDF目录224604 > NT5TU64M16DG-3C (NANYA TECHNOLOGY CORP) 64M X 16 DDR DRAM, 0.45 ns, PBGA84 PDF资料下载
参数资料
| 型号： | NT5TU64M16DG-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | GREEN, BGA-84 |
| 文件页数： | 5/85页 |
| 文件大小： | 2622K |
| 代理商： | NT5TU64M16DG-3C |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
13
REV 1.0
06 / 2010
- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must
be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to
VDDQ.)
- Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ ≧ VREF must be met at all time.
- Apply VTT.
2. Start clock (CK,
) and maintain stable condition.
3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and
maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or
Deselect & take CKE HIGH.
4. Waiting minimum of 400ns then issue pre-charge all command. NOP or Deselect applied during 400ns period.
5. Issue an EMRS command to EMR (2). (Provide LOW to BA0 and BA2, and HIGH to BA1).
6. Issue an EMRS command to EMR (3). (Provide LOW to BA2 and HIGH to BA0 and BA1).
7. Issue EMRS to enable DLL. (Provide Low to A0, HIGH to BA0 and LOW to BA1-BA2 and A13-A15. And
A9=A8=A7=LOW must be used when issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (Provide HIGH to A8 and LOW to BA0-BA2, and A13-A15.)
9. Issue a precharge all command.
10. Issue 2 more auto-refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without
resetting the DLL.)
12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration
is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit
OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 DRAM is now ready for normal operation.
* To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
Example
CK, CK
1st Auto
refresh
MRS
PRE
ALL
EMRS
CMD
2nd Auto
refresh
tRP
tRFC
Extended Mode
Register Set
with DLL enable
Mode Register Set
with DLL reset
PRE
ALL
tMRD
min. 200 cycles to
lock the DLL
CKE
Command
400 ns
MRS
NOP
tMRD
EMRS
Follow OCD
flowchart
ODT "low"
Follow OCD
flowchart
EMRS
相关PDF资料 |
PDF描述 |
|---|---|
| NTA2425E | |
| NTA2425F | |
| NTA2410-10 | |
| NTD2410F | |
| NTA2425-10 | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙铁 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 产品:Soldering Stations 类型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大温度:+ 850 F 电缆类型:US Cord Included |
发布紧急采购，3分钟左右您将得到回复。