参数资料
型号: NT5TU64M16DG-3C
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封装: GREEN, BGA-84
文件页数: 16/85页
文件大小: 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
23
REV 1.0
06 / 2010
Drive Mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD
impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers
are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
NOP
EMRS(1)
CMD
DQ_in
NOP
DQS_in
CK, CK
EMRS(1)
NOP
Enter Drive Mode
OCD calibration
mode exit
NOP
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
DQS high for Drive(0)
DQS high for Drive(1)
tOIT
On-Die Termination (ODT)
ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS,
, RDQS, , and DM signal for x8 configurations via the ODT control pin. For x16 configuration ODT is applied to
each DQ, UDQS,
, LDQS, , UDM and LDM signal via the ODT control pin. The ODT feature is designed to
improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination
resistance for any or all DRAM devices.
The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode.
Functional Representation of ODT
DRAM
Input
Buffer
Input
Pin
Rval1
Rval2
sw1
sw2
VDDQ
VSSQ
Rval3
sw3
VDDQ
VSSQ
Switch sw1, sw2, or sw3 is enabled by the ODT pin. Selection between sw1, sw2, or sw3 is determined by “Rtt (nominal)” in EMRS.
Termination included on all DQs, DM, DQS,
, RDQS, and pins.
相关PDF资料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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