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| 型号： | NT5TU64M16DG-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | GREEN, BGA-84 |
| 文件页数： | 4/85页 |
| 文件大小： | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
12
REV 1.0
06 / 2010
Functional Description
The 1Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. The
1Gb DDR SDRAM is internally configured as a octal-bank DRAM.
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for
the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command,
which is followed by a Read or Write command. The address bits registered coincident with the activate command are
used to select the bank and row to be accesses (BA0, BA1, & BA2 select the banks, A0-A13 select the row for x4 and x8
components, A0-A12 select the row for x16 components). The address bits registered coincident with the Read or Write
command are used to select the starting column location for the burst access and to determine if the Auto-Precharge
command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
Power-up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation.
The following sequence is required for POWER UP and Initialization.
1. Either one of the following sequence is required for Power-up.
While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be unde-
fined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and
during the VDD voltage ramp up, IVDD-VDDQI≦0.3 volts. Once the ramping of the supply voltages is complete (when
VDDQ crosses VDDQ min), the supply voltage specifications in Re-commanded DC operating conditions table.
- VDD, VDDL, and VDDQ are driven from a signal power converter output, AND
- VTT is limited to 0.95V max, AND
- Vref tracks VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ>=VREF must be met at all times.
While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be
undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up.
During the ramping of the supply voltages, VDD≧VDDL≧VDDQ must be maintained and is applicable to both AC and
DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the
ramping of the supply voltages is complete, the supply voltage specifications provided in Re-commanded DC operating
conditions table.
- Apply VDD/VDDL before or at the same time as VDDQ.
- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin.
- Apply VDDQ before or at the same time as VTT.
相关PDF资料 |
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| NTA2425E | |
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| NTA2410-10 | |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙铁 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 产品:Soldering Stations 类型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大温度:+ 850 F 电缆类型:US Cord Included |
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