参数资料
型号: NTHD4508NT1G
厂商: ON Semiconductor
文件页数: 5/6页
文件大小: 0K
描述: MOSFET 2N-CH 20V 3.1A CHIPFET
产品目录绘图: MOSFET ChipFET
标准包装: 10
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 3A
开态Rds(最大)@ Id, Vgs @ 25° C: 75 毫欧 @ 3.1A,4.5V
Id 时的 Vgs(th)(最大): 1.2V @ 250µA
闸电荷(Qg) @ Vgs: 4nC @ 4.5V
输入电容 (Ciss) @ Vds: 180pF @ 10V
功率 - 最大: 1.13W
安装类型: 表面贴装
封装/外壳: 8-SMD,扁平引线
供应商设备封装: ChipFET?
包装: 标准包装
产品目录页面: 1558 (CN2011-ZH PDF)
其它名称: NTHD4508NT1GOSDKR
NTHD4508N
SOLDERING FOOTPRINTS*
0.45 7
2.03 2
0.08
2.03 2
0.08
0.018
0.63 5
0.025
0.63 5
0.025
1.03 2
0.043
0.17 8
0.007
0.45 7
0.018
0.66
0.026
0.711
0.028
0.66
0.026
0.25 4
0.010
SCALE 20:1
mm
inches
Figure 11. Basic
Figure 12. Style 2
*For additional information on our Pb?Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 11. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in Figure
12 improves the thermal area of the drain connections (pins
footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq.
mm). This will assist the power dissipation path away from
the device (through the copper lead?frame) and into the
board and exterior chassis (if applicable) for the single
device. The addition of a further copper area and/or the
addition of vias to other board layers will enhance the
performance still further.
5, 6, 7, 8) while remaining within the confines of the basic
http://onsemi.com
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