参数资料
型号: NTLTD7900ZR2G
厂商: ON Semiconductor
文件页数: 1/8页
文件大小: 0K
描述: MOSFET PWR N-CHAN 9A 20V 8MICRO
产品变化通告: Product Obsolescence 21/Jan/2010
标准包装: 1
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 6A
开态Rds(最大)@ Id, Vgs @ 25° C: 26 毫欧 @ 6.5A,4.5V
Id 时的 Vgs(th)(最大): 1V @ 250µA
闸电荷(Qg) @ Vgs: 18nC @ 4.5V
输入电容 (Ciss) @ Vds: 15pF @ 16V
功率 - 最大: 1.5W
安装类型: 表面贴装
封装/外壳: 8-VDFN 裸露焊盘
供应商设备封装: Micro8?
包装: 剪切带 (CT)
其它名称: NTLTD7900ZR2GOSCT
NTLTD7900ZR2
Power MOSFET
9 A, 20 V, Logic Level, N--Channel
Micro8 ? Leadless
This advanced Power MOSFET contains monolithic back--to--back
Zener diodes. These Zener diodes provide protection against ESD and
unexpected transients. These miniature surface mount MOSFETs
feature ultra low R DS(on) and true logic level performance. This device
is designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are DC--DC
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
Features
? Pb--Free Package is Available
http://onsemi.com
9 AMPERES
20 VOLTS
R DS(on) = 26 m Ω
(V GS = 4.5 V, I D = 6.5 A)
R DS(on) = 31 m Ω
(V GS = 2.5 V, I D = 5.8 A)
Applications
? Zener Protected Gates Provide Electrostatic Discharge Protection
? Designed to Withstand 4000 V Human Body Model
D
D
? Ultra Low R DS(on) Provides Higher Efficiency and Extends
Battery Life
? Logic Level Gate Drive -- Can be Driven by Logic ICs
G 1
2.4 k Ω
G 2
2.4 k Ω
? Micro8 Leadless Surface Mount Package -- Saves Board Space
? I DSS Specified at Elevated Temperature
N--Channel
S 1
N--Channel
S 2
MAXIMUM RATINGS (T J = 25 ° C unless otherwise noted)
Steady
MARKING DIAGRAM
7900
Rating
Drain--to--Source Voltage
Gate--to--Source Voltage
Continuous Drain Current (Note 1)
T A = 25 ° C
T A = 85 ° C
Pulsed Drain Current
(tp ≤ 10 m s)
Continuous Source--Diode
Conduction (Note 1)
Symbol
V DSS
V GS
I D
I DM
I s
10 Sec
9.0
6.4
2.9
20
± 12
30
State
6.0
4.3
1.4
Unit
V
V
A
A
A
1
Micro8 LEADLESS
CASE 846C
A
Y
WW
G
1
AYWW
G
= Assembly Location
= Year
= Work Week
= Pb--Free Package
Total Power Dissipation (Note 1)
T A = 25 ° C
T A = 85 ° C
P D
3.2
1.7
1.5
0.79
W
Drain
PIN ASSIGNMEN T
8 1
Source 1
Operating Junction and Storage
Temperature Range
Thermal Resistance (Note 1)
Junction--to--Ambient
T J , T stg
R θ JA
--55 to 150
38 82
° C
° C/W
Drain
Drain
Drain
7
6
5
Drain
2
3
4
Gate 1
Source 2
Gate 2
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to 1 ″ x 1 ″ FR--4 board.
(Bottom View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
? Semiconductor Components Industries, LLC, 2009
October, 2009 -- Rev. 7
1
Publication Order Number:
NTLTD7900ZR2/D
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