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参数资料
| 型号： | NTQS6463R2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 20V 6.8A 8-TSSOP |
| 产品变化通告： | Product Discontinuation 02/Jan/2007 |
| 标准包装： | 4,000 |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 6.8A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 20 毫欧 @ 6.8A，4.5V |
| Id 时的 Vgs(th)（最大）： | 900mV @ 250µA |
| 闸电荷(Qg) @ Vgs： | 50nC @ 5V |
| 功率 - 最大： | 1.39W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | NTQS6463R2OS |
NTQS6463
5
4
QT
V GS = ?4.5
1000
V DD = ?16 V
I D = ?6.8 A
V GS = ?4.5 V
t f
3
t d(off)
t r
2
1
0
Q1
Q2
T J = 25 ° C
I D = ?6.8 A
100
10
t d(on)
0
4
8
12
16
20
24
28
1
10
100
Q g , TOTAL GATE CHARGE (nC)
Figure 8. Gate?to?Source and
Drain?to?Source Voltage versus Total Charge
100
R G , GATE RESISTANCE ( W )
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Mounted on 2 ″ sq. FR4 board (1 ″ sq. 1 oz. Cu 0.06 ″ thick single sided)
1.2
V GS = 0 V
T J = 25 ° C
10
10 m s
100 m s
1 ms
0.8
1
V GS = ?4.5 V
10 ms
0.4
0.1
SINGLE PULSE
T C = 25 ° C
R DS(on) LIMIT
dc
THERMAL LIMIT
0
0.4
0.5
0.6
0.7
0.01
0.1
PACKAGE LIMIT
1
10
100
?V SD , SOURCE?TO?DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
Current
V DS , DRAIN?TO?SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain?to?source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T C ) of 25 ° C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance ?
General Data and Its Use.”
Switching between the off?state and the on?state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded and the
transition time (t r , t f ) do not exceed 10 m s. In addition the
total power averaged over a complete switching cycle must
not exceed (T J(MAX) ? T C )/(R θ JC ).
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non?linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E?FETs can withstand the stress of
drain?to?source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (I D ), in accordance with industry
custom. The energy rating must be derated for temperature.
Maximum energy at currents below rated continuous I D can
safely be assumed to equal the values indicated.
A Power MOSFET designated E?FET can be safely used
in switching circuits with unclamped inductive loads. For
http://onsemi.com
5
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