参数资料
| 型号： | OPENLPPOL-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 10/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL OPEN-LOOP POL |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电流感应 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | Si8410，Si8512，Si8540 |
| 主要属性： | 单相 POL，100 ~ 500 kHz 切换频率 |
| 次要属性： | 20 ~ 80% 可变占空比 |
| 已供物品： | 板 |
| 产品目录页面： | 628 (CN2011-ZH PDF) |
| 其它名称： | 336-1919 |
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Si85xx
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FAULT output (Si8517/8/9): Goes low when
external reset timing is in error.
Ease-of-use: Other than conventional power and
grounding techniques, no special board layout
considerations are required. Built-in timing interface
circuits allow already-available system switching
signals to be used for reset with no external circuits
required.
2.3. Integrator Reset and
Current Measurement
The Si85xx measures current flowing from the IIN to
IOUT terminals. Current is allowed to flow in the
opposite direction, but will not be measured (OUT1 and
OUT 2 remain at their minimum values during reverse
current flow. Reverse current flow will not damage the
Si85xx).
2.1. Under Voltage Lockout (UVLO)
UVLO is provided to prevent erroneous operation during
device start-up and shutdown or when VDD is
significantly below the specified operating range. The
Si85xx is in UVLO state when VDD < V UVLO (Figure 4).
During UVLO, the output(s) are held at minimum value
regardless of the amount of current flowing from IIN to
IOUT, and signals on integrator reset inputs R1–R4 are
ignored. The Si85xx exits UVLO when VDD > (V UVLO +
V HYST ).
2.2. Device Startup
Upon exit from UVLO, the Si85xx performs a voltage
offset and temperature self-calibration cycle. During this
time, output(s) are held at minimum value and reset
inputs (R1-R4) are ignored. The reset inputs are
enabled at the end of the self-calibration cycle, and an
integrator reset cycle is initiated on the first occurrence
of active signals on R1–R4. A current measurement is
initiated immediately after the completion of the
integrator reset cycle, and the resulting current
waveforms appear on the output pins. This "reset-
measure-reset" pattern repeats throughout steady-state
operation.
V UVLO + V HYST
To achieve the specified accuracy, the integrator
capacitor must be discharged (reset) for time period t R
prior to the start of every measurement cycle. This
cycle-by-cycle reset is implemented by connecting
existing system gate control signals to the R1–R4 inputs
in a way that resets the integrator when no current is
flowing from IIN to IOUT. To achieve rated accuracy, the
reset cycle must be completed prior to the start of the
measurement cycle. For maximum flexibility, integrator
reset operation can be configured in one of two ways:
Option 1: The start and duration of reset is
determined by the states of the timing
signals applied to R1–R4.
Option 2: The timing signals applied to R1–R4 trigger
the start of reset, and the duration of the
reset is determined by an onboard
programmable reset timer.
VDD
SUPPLY
First Positive Edge
Following End of Self-Cal
INTEGRATOR
DON’T CARE
tRP
tRP
RESET
Si85xx
STATUS
UNDER VOLTAGE
LOCKOUT STATE
START-UP
SELF-CAL CYCLE
RESET
MEASURE CURRENT
RESET
tCAL
tR
tR
10
Si85xx
OUTPUT
VOUT MIN
OUT1, OUT2
VALID
Figure 4. Si85xx Startup and Control Timing
Preliminary Rev. 0.4
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