参数资料
| 型号： | OPENLPPOL-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL OPEN-LOOP POL |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电流感应 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | Si8410，Si8512，Si8540 |
| 主要属性： | 单相 POL，100 ~ 500 kHz 切换频率 |
| 次要属性： | 20 ~ 80% 可变占空比 |
| 已供物品： | 板 |
| 产品目录页面： | 628 (CN2011-ZH PDF) |
| 其它名称： | 336-1919 |
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Si85xx
3.3. Device Configuration
Configuring the Si85xx involves the following steps:
1. Selecting an output mode
2. Configuring integrator reset timing
3. Setting integrator reset time t R
R1
R2
3.3.1. Device Selection
The Si85xx family offers three output modes: Single
Si85xx State
MEASURE RESET
tR
MEASURE RESET
tR
output (Si850x), and 2 and 4-Wire Ping Pong (Si851x).
The Si851x products can be configured to operate in all
three of these output modes.
The Si850x products operate ONLY in Single output
mode. Most half-wave and single-phase applications
require only Single output mode and will typically use
the Si850x.
In Single output mode, output current always appears
on the OUT pin (Si850x) or the OUT1 pin (Si851x). A
single integrator reset signal is typically sufficient when
operating in this mode.
Ping-Pong mode routes the current waveform to two
different output pins on alternate measurement cycles.
It is useful in full-wave and push-pull topologies where
external circuitry can be used to monitor and/or control
transformer flux balance. (Section "3. Application
both output modes in various power topologies.)
2-wire Ping-Pong mode is useful mainly in non-
overlapping two-phase buck converters but may also be
used in full-bridge applications. In this output mode,
reset inputs R1 and R2 are used, and input R3 is
grounded. Measured current appears on OUT1 when
R1 is high and on OUT2 when R2 is high as shown in
the full-bridge timing example of Figures 11 and 12.
R1
OUT1
OUT2
TIME
Figure 12. Full-Bridge Timing Example B
4-Wire Ping-Pong mode is recommended for full-bridge
applications over 2-wire because it uses all four inputs,
making the reset function tolerant to single-point signal
failures. In 4-Wire Ping-Pong mode, current appears on
OUT2 when R1 is high and R2 is low, and appears on
OUT1 when R3 is high and R4 is low as shown in the
full-bridge timing example of Figure 13. Table 11 shows
the states of the Mode and R4 inputs that select each
output, and the resulting reset logic functions and truth
tables.
R1
R2
R3
R2
R4
Si85xx State
MEASURE RESET
tR
MEASURE RESET
tR
MEASURE RESET
MEASURE RESET
OUT1
OUT2
TIME
OUT1
tR
tR
Figure 11. Two-Phase Buck Timing Example A
OUT2
Figure 13. Full-Bridge Timing Example C
14
Preliminary Rev. 0.4
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