参数资料
| 型号： | OPENLPPOL-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL OPEN-LOOP POL |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电流感应 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | Si8410，Si8512，Si8540 |
| 主要属性： | 单相 POL，100 ~ 500 kHz 切换频率 |
| 次要属性： | 20 ~ 80% 可变占空比 |
| 已供物品： | 板 |
| 产品目录页面： | 628 (CN2011-ZH PDF) |
| 其它名称： | 336-1919 |
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Si85xx
3.3.2. Selecting Reset Timing Signals
Reset timing signals should be chosen to meet the
following conditions:
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Satisfy reset time t R
Not overlap integrator reset into the desired
measurement period
Not violate reset watchdog timeout period t WD
3.3.3. Configuring Integrator Reset
Per Section “2. Functional Overview”, the integrator
must be reset (zeroed) prior to the start of each
measurement cycle to achieve specified measurement
accuracy. This reset must be synchronized with the
system switch timing signals to ensure that current is
measured during the appropriate time; so, the Si85xx
integrator reset circuitry uses system timing as its
reference. Timing signals connect to reset inputs R1
through R4 where built-in logic functions allow the user
to choose the conditions that cause an integrator reset
event. Important Note: reset inputs R1–R4 are rated to
a maximum input voltage of VDD. External resistor
dividers must be used when connecting driver output
signals to R1–R4 that swing beyond VDD.
As shown in Table 11, the Si850x integrator reset logic
is a simple XOR gate where reset is maintained (or
triggered, depending on use of the TRST input) when
states of reset inputs R1 and R2 are not equal.
where any one of three reset logic functions can cause
integrator reset. The output mode (Si851x) is
determined by the states of the Mode and R4 inputs, as
Preliminary Rev. 0.4
15
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