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| 型号： | OR3T55-4BA256 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 112/210页 |
| 文件大小： | 2138K |
| 代理商： | OR3T55-4BA256 |
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Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Contents
Page
Features .......................................................................... 1
System-Level Features ................................................... 3
Description ...................................................................... 4
FPGA Overview .......................................................... 4
PLC Logic ................................................................... 4
PIC Logic .................................................................... 5
System Features ......................................................... 5
Routing ....................................................................... 5
Configuration .............................................................. 5
ORCA Foundry Development System ........................ 6
Architecture ..................................................................... 6
Programmable Logic Cells .............................................. 8
Programmable Function Unit ...................................... 8
Look-Up Table Operating Modes .............................. 10
Supplemental Logic and Interconnect
Cell (SLIC) ............................................................ 18
PLC Latches/Flip-Flops ............................................ 22
PLC Routing Resources ........................................... 24
PLC Architectural Description ................................... 31
Programmable Input/Output Cells ................................ 33
5 V Tolerant I/O ......................................................... 34
PCI Compliant I/O ..................................................... 34
Inputs ........................................................................ 35
Outputs ..................................................................... 38
PIC Routing Resources ............................................ 41
PIC Architectural Description .................................... 42
High-Level Routing Resources ..................................... 44
Interquad Routing ..................................................... 44
Programmable Corner Cell Routing .......................... 45
PIC Interquad (MID) Routing .................................... 46
Clock Distribution Network ............................................ 47
PFU Clock Sources .................................................. 47
Clock Distribution in the PLC Array .......................... 48
Clock Sources to the PLC Array ............................... 49
Clocks in the PICs .................................................... 49
ExpressCLK Inputs ................................................... 50
Selecting Clock Input Pins ........................................ 50
Special Function Blocks ................................................ 51
Single Function Blocks ............................................. 51
Boundary Scan ......................................................... 54
Microprocessor Interface (MPI) .................................... 61
PowerPC System ...................................................... 62
i960 System .............................................................. 63
MPI Interface to FPGA .............................................. 64
MPI Setup and Control ............................................. 65
Programmable Clock Manager
(PCM): (Advance Information) ....................................... 69
PCM Registers .......................................................... 70
Delay-Locked Loop (DLL) Mode ............................... 72
Phase-Locked Loop (PLL) Mode .............................. 73
PCM/FPGA Internal Interface ................................... 75
PCM Operation ......................................................... 75
PCM Detailed Programming ..................................... 76
PCM Applications ..................................................... 79
PCM Cautions ........................................................... 80
FPGA States of Operation ............................................ 81
Initialization ............................................................... 81
Configuration ............................................................ 82
Start-Up .................................................................... 83
Reconfiguration ......................................................... 84
Partial Reconfiguration .............................................. 84
Other Configuration Options ..................................... 84
Configuration Data Format ............................................ 85
Using
ORCA Foundry to Generate
Configuration RAM Data ....................................... 85
Configuration Data Frame ......................................... 85
Bit Stream Error Checking ........................................ 87
FPGA Configuration Modes .......................................... 88
Master Parallel Mode ................................................ 88
Master Serial Mode ................................................... 89
Asynchronous Peripheral Mode ................................ 90
Microprocessor Interface (MPI) Mode ....................... 90
Slave Serial Mode ..................................................... 93
Slave Parallel Mode .................................................. 93
Daisy-Chaining .......................................................... 94
Daisy-Chaining with Boundary Scan.......................... 95
Absolute Maximum Ratings .......................................... 95
Recommended Operating Conditions ........................... 95
Electrical Characteristics ............................................... 96
Timing Characteristics ................................................... 98
Description ................................................................ 98
PFU Timing ............................................................. 100
PLC Timing ............................................................. 107
SLIC Timing ............................................................ 107
PIO Timing .............................................................. 108
Special Function Blocks Timing ...............................111
Clock Timing ........................................................... 118
Configuration Timing ............................................... 125
Readback Timing .................................................... 135
Input/Output Buffer Measurement Conditions ............. 136
Output Buffer Characteristics ...................................... 137
OR3Cxx .................................................................. 137
OR3Txxx ................................................................. 138
Estimating Power Dissipation ..................................... 139
OR3Cxx .................................................................. 139
OR3Txxx ................................................................. 140
PCM Power Dissipation ........................................... 141
Pin Information ............................................................ 142
Pin Descriptions ...................................................... 142
Package Compatibility ............................................ 146
Compatibility with OR2C/TxxA Series ..................... 147
Package Thermal Characteristics ................................ 194
ΘJA .......................................................................... 194
ψ JC ......................................................................... 194
ΘJC .......................................................................... 194
ΘJB .......................................................................... 194
FPGA Maximum Junction Temperature ................... 195
Package Coplanarity .................................................... 196
Package Parasitics ...................................................... 196
Package Outline Diagrams .......................................... 197
Terms and Definitions .............................................. 197
208-Pin SQFP.......................................................... 198
208-Pin SQFP2........................................................ 199
240-Pin SQPF.......................................................... 200
240-Pin SQFP2........................................................ 201
256-Pin PBGA.......................................................... 202
352-Pin PBGA.......................................................... 203
432-Pin EBGA.......................................................... 204
600-Pin EBGA.......................................................... 205
Index ............................................................................ 206
Ordering Information ................................................... 209
相关PDF资料 |
PDF描述 |
|---|---|
| OR3T55-4BA352I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352 |
| OR3T55-4BA352 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352 |
| OR3T80-4BA352I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
| OR3T80-4BA352 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
| OR3T125-4BC432I | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PBGA432 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR3T55-4BA256I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-4PS208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-4PS240I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-5BA256 | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5BA256I | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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