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参数资料

型号：	P0037
厂商：	Terasic Technologies Inc
文件页数：	19/34页
文件大小：	0K
描述：	BOARD DEV/EDUCATION ALTERA DE0
产品培训模块：	Cyclone® III FPGA
标准包装：	1
类型：	FPGA
适用于相关产品：	Cyclone III
所含物品：	板，线缆，CD，电源
相关产品：	544-2541-ND - IC CYCLONE III FPGA 16K 164 MBGA 544-2540-ND - IC CYCLONE III FPGA 16K 144 EQFP 544-2480-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2478-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2477-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2476-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2474-ND - IC CYCLONE III FPGA 16K 484FBGA 544-2473-ND - IC CYCLONE III FPGA 16K 484FBGA 544-2472-ND - IC CYCLONE III FPGA 16K 484FBGA 544-2471-ND - IC CYCLONE III FPGA 16K 484FBGA 更多...

Chapter 1: Cyclone III Device Datasheet

Switching Characteristics

Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 2 of 2)

1–19

C6

C7, I7

C8, A7

Symbol

Modes

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

×10

×8

100

80

—

—

170

170

100

80

—

—

170

170

100

80

—

—

170

170

Mbps

Mbps

Device

operation in

Mbps

t DUTY

TCCS

×7

×4

×2

×1

—

—

70

40

20

10

45

—

—

—

—

—

—

—

170

170

170

170

55

200

70

40

20

10

45

—

—

—

—

—

—

—

170

170

170

170

55

200

70

40

20

10

45

—

—

—

—

—

—

—

170

170

170

170

55

200

Mbps

Mbps

Mbps

Mbps

%

ps

Output jitter

(peak to

—

—

—

500

—

—

500

—

—

550

ps

peak)

t RISE

t FALL

20 – 80%,

C LOAD = 5 pF

20 – 80%,

C LOAD = 5 pF

—

—

500

500

—

—

—

—

500

500

—

—

—

—

500

500

—

—

ps

ps

t LOCK

—

—

—

1

—

—

1

—

—

1

ms

Notes to Table 1–27 :

(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.

(2) t LOCK is the time required for the PLL to lock from the end of device configuration.

Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1) ,

(Part 1 of 2)

C6

C7, I7

C8, A7

Symbol

Modes

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

×10

×8

5

5

—

—

200

200

5

5

—

—

155.5

155.5

5

5

—

—

155.5

155.5

MHz

MHz

f HSCLK (input

clock

frequency)

Device

operation in

Mbps

t DUTY

TCCS

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

—

5

5

5

5

100

80

70

40

20

10

45

—

—

—

—

—

—

—

—

—

—

—

—

—

200

200

200

400

400

400

400

400

400

400

55

200

5

5

5

5

100

80

70

40

20

10

45

—

—

—

—

—

—

—

—

—

—

—

—

—

155.5

155.5

155.5

311

311

311

311

311

311

311

55

200

5

5

5

5

100

80

70

40

20

10

45

—

—

—

—

—

—

—

—

—

—

—

—

—

155.5

155.5

155.5

311

311

311

311

311

311

311

55

200

MHz

MHz

MHz

MHz

Mbps

Mbps

Mbps

Mbps

Mbps

Mbps

%

ps

July 2012

Altera Corporation

Cyclone III Device Handbook

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