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| 型号： | P0037 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 29/34页 |
| 文件大小： | 0K |
| 描述： | BOARD DEV/EDUCATION ALTERA DE0 |
| 产品培训模块： | Cyclone® III FPGA |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone III |
| 所含物品： | 板，线缆，CD，电源 |
| 相关产品： | 544-2541-ND - IC CYCLONE III FPGA 16K 164 MBGA 544-2540-ND - IC CYCLONE III FPGA 16K 144 EQFP 544-2480-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2478-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2477-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2476-ND - IC CYCLONE III FPGA 16K 484UBGA 544-2474-ND - IC CYCLONE III FPGA 16K 484FBGA 544-2473-ND - IC CYCLONE III FPGA 16K 484FBGA 544-2472-ND - IC CYCLONE III FPGA 16K 484FBGA 544-2471-ND - IC CYCLONE III FPGA 16K 484FBGA 更多... |
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Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 3 of 5)
1–29
Letter
Term
V OH
Definitions
V IH(DC)
V IH (AC )
V CCIO
Single-ended
Voltage
V REF
V IL(DC)
V IL(AC )
S
referenced I/O
Standard
V OL
V SS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing .
SW (Sampling
Window)
t C
TCCS (Channel-
to-channel-skew)
tcin
t CO
tcout
t DUTY
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
including t CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
T
July 2012
t FALL
t H
Timing Unit
Interval (TUI)
t INJITTER
t OUTJITTER_DEDCLK
t OUTJITTER_IO
tpllcin
tpllcout
Altera Corporation
Signal High-to-low transition time (80–20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t C /w).
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P0037 (ACADEMIC) | 制造商:Terasic 功能描述:(DE0) 3C16 - ACADEMIC PRICE |
| P0038 | 功能描述:子卡和OEM板 ETHERNET - HSMC CARD (HSMC-NET) RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| P0039 | 功能描述:子卡和OEM板 SDI - HSMC CARD (SDI-HSMC) RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| P003KDKB | 制造商:Hammond Power Solutions 功能描述:POTTED 3PH N3R CU CLASS 1, DIV II 3kVA 480-240 |
| P0040 | 功能描述:子卡和OEM板 SFP - HSMC CARD (SFP-HSMC) RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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