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参数资料
| 型号： | P89V52X2FBD,157 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 19/57页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 44-LQFP |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 800 |
| 系列： | 89V |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | UART/USART |
| 外围设备： | POR |
| 输入/输出数： | 32 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LQFP |
| 包装： | 托盘 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名称： | 568-4250 935282529157 P89V52X2FBD |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
26 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.10.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB rst), and a stop bit (logical 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1
2 overow rate.
6.10.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8
data bits (LSB rst), a programmable 9th data bit, and a stop bit (logical 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the
parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The
baud rate is programmable to either 1
16 or
1
32 of the CPU clock frequency, as determined
by the SMOD1 bit in PCON.
6.10.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB rst), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3
is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is
variable and is determined by the Timer 1
2 overow rate.
Table 21.
SCON - Serial port control register (address 98H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Table 22.
SCON - Serial port control register (address 98H) bit description
Bit
Symbol
Description
7
SM0/FE
The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, denes the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to ‘1’.)
6
SM1
With SM0, denes the serial port mode (see Table 23 below).
5
SM2
Enables the multiprocessor communication feature in Modes 2 and 3.
In Mode 2 or 3, if SM2 is set to ‘1’, then RI will not be activated if the
received 9th data bit (RB8) is ‘0’. In Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In Mode 0, SM2
should be ‘0’.
4
REN
Enables serial reception. Set by software to enable reception. Clear by
software to disable reception.
3
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear
by software as desired.
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