参数资料
型号: P89V52X2FBD,157
厂商: NXP Semiconductors
文件页数: 20/57页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 44-LQFP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 800
系列: 89V
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 192 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1012-ND - BOARD FOR P89V52X2 44-TQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
其它名称: 568-4250
935282529157
P89V52X2FBD
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
27 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.10.5 Framing error
Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,
SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0
is set to ‘1’.
6.10.6 More about UART mode 1
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition
is detected, the divide-by-16 counter is immediately reset to align its rollovers with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th
counter states of each bit time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise
rejection. If the value accepted during the rst bit time is not 0, the receive circuits are
reset and the unit goes back to looking for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the nal shift pulse is generated: (a) RI = 0, and
(b) Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both
conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is
activated.
6.10.7 More about UART modes 2 and 3
Reception is performed in the same manner as in mode 1.
2
RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it
SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is
undened.
1
TI
Transmit interrupt ag. Set by hardware at the end of the 8th bit time in
Mode 0, or at the stop bit in the other modes, in any serial
transmission. Must be cleared by software.
0
RI
Receive interrupt ag. Set by hardware at the end of the 8th bit time in
Mode 0, or approximately halfway through the stop bit time in all other
modes. (See SM2 for exceptions). Must be cleared by software.
Table 23.
SCON - Serial port control register (address 98H) SM0/SM1 mode denition
SM0, SM1
UART mode
Baud rate
0 0
0: shift register
CPU clock/6
0 1
1: 8-bit UART
variable
1 0
2: 9-bit UART
CPU clock/32 or CPU clock/16
1 1
3: 9-bit UART
variable
Table 22.
SCON - Serial port control register (address 98H) bit description …continued
Bit
Symbol
Description
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